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Class Information
Number: 712/300
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Byte-word rearranging, bit-field insertion or extraction, string length detecting, or sequence detecting
Description: Subject matter having means or step for shuffling, adding, removing of bit or for recognizing a sequence of bytes in a larger string of bytes not provided for by the subclasses above.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7434040 |
Copying of unaligned data in a pipelined operation |
Oct. 7, 2008 |
| 7424600 |
Information processing apparatus, information processing method, and program conversion apparatus, in which stack memory is used with improved efficiency |
Sep. 9, 2008 |
| 7403835 |
Device and method for programming an industrial robot |
Jul. 22, 2008 |
| 7395412 |
Apparatus and method for extending data modes in a microprocessor |
Jul. 1, 2008 |
| 7389408 |
Microarchitecture for compact storage of embedded constants |
Jun. 17, 2008 |
| 7386699 |
Aligning IP payloads on memory boundaries for improved performance at a switch |
Jun. 10, 2008 |
| 7370184 |
Shifter for alignment with bit formatter gating bits from shifted operand, shifted carry operand and most significant bit |
May. 6, 2008 |
| 7363478 |
Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index |
Apr. 22, 2008 |
| 7356676 |
Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register |
Apr. 8, 2008 |
| 7353371 |
Circuit to extract nonadjacent bits from data packets |
Apr. 1, 2008 |
| 7350058 |
Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register |
Mar. 25, 2008 |
| 7346430 |
Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatus |
Mar. 18, 2008 |
| 7340588 |
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code |
Mar. 4, 2008 |
| 7334116 |
Bit manipulation on data in a bitstream that is stored in a memory having an address boundary length |
Feb. 19, 2008 |
| 7315261 |
Method for converting data from pixel format to bitplane format |
Jan. 1, 2008 |
| 7315937 |
Microprocessor instructions for efficient bit stream extractions |
Jan. 1, 2008 |
| 7313660 |
Data stream frequency reduction and/or phase shift |
Dec. 25, 2007 |
| 7277574 |
Methods and systems for feature selection |
Oct. 2, 2007 |
| 7275147 |
Method and apparatus for data alignment and parsing in SIMD computer architecture |
Sep. 25, 2007 |
| 7269478 |
Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatus |
Sep. 11, 2007 |
| 7269477 |
Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatus |
Sep. 11, 2007 |
| 7263563 |
Multi-bus driver apparatus and method for driving a plurality of buses |
Aug. 28, 2007 |
| 7260711 |
Single instruction multiple data processing allowing the combination of portions of two data words with a single pack instruction |
Aug. 21, 2007 |
| 7257697 |
Processing system with general purpose execution unit and separate independently operating data string manipulation unit |
Aug. 14, 2007 |
| 7254699 |
Aligning load/store data using rotate, mask, zero/sign-extend and or operation |
Aug. 7, 2007 |
| 7251722 |
Semantic processor storage server architecture |
Jul. 31, 2007 |
| 7237097 |
Partial bitwise permutations |
Jun. 26, 2007 |
| 7231505 |
Aligning IP payloads on memory boundaries for improved performance at a switch |
Jun. 12, 2007 |
| 7210134 |
Deterring reverse-engineering of software systems by randomizing the siting of stack-based data |
Apr. 24, 2007 |
| 7210023 |
Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated w |
Apr. 24, 2007 |
| 7188115 |
Processing fixed-format data in a unicode environment |
Mar. 6, 2007 |
| 7155601 |
Multi-element operand sub-portion shuffle instruction execution |
Dec. 26, 2006 |
| 7143231 |
Method and apparatus for performing packet classification for policy-based packet routing |
Nov. 28, 2006 |
| 7139904 |
Data byte insertion circuitry |
Nov. 21, 2006 |
| 7139905 |
Dynamic endian switching |
Nov. 21, 2006 |
| 7133040 |
System and method for performing an insert-extract instruction |
Nov. 7, 2006 |
| 7127595 |
Method and system for configuring to a desired order the order of a data array |
Oct. 24, 2006 |
| 7114055 |
Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word |
Sep. 26, 2006 |
| 7110860 |
Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatus |
Sep. 19, 2006 |
| 7100029 |
Performing repeat string operations |
Aug. 29, 2006 |
| 7085935 |
Managing a secure environment using a chipset in isolated execution mode |
Aug. 1, 2006 |
| 7062637 |
DSP operations with permutation of vector complex data type operands |
Jun. 13, 2006 |
| 7054964 |
Method and system for bit-based data access |
May. 30, 2006 |
| 7051195 |
Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset |
May. 23, 2006 |
| 7051168 |
Method and apparatus for aligning memory write data in a microprocessor |
May. 23, 2006 |
| 7050884 |
Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatus |
May. 23, 2006 |
| 7047396 |
Fixed length memory to memory arithmetic and architecture for a communications embedded processor system |
May. 16, 2006 |
| 7047383 |
Byte swap operation for a 64 bit operand |
May. 16, 2006 |
| 7039795 |
System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data |
May. 2, 2006 |
| 7015718 |
Register file apparatus and method for computing flush masks in a multi-threaded processing system |
Mar. 21, 2006 |
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