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Class Information
Number: 712/27
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Data driven or demand driven processor > Particular data driven memory structure
Description: Subject matter including a data driven interface with specific memory structure to enhance the data flow capability of the processor.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7545896 |
Asynchronous multi-clock system |
Jun. 9, 2009 |
| 7493469 |
Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium |
Feb. 17, 2009 |
| 7480679 |
Duplicated naming service in a distributed processing system |
Jan. 20, 2009 |
| 7467286 |
Executing partial-width packed data instructions |
Dec. 16, 2008 |
| 7315932 |
Data processing system having instruction specifiers for SIMD register operands and method thereof |
Jan. 1, 2008 |
| 7278013 |
Apparatus having a cache and a loop buffer |
Oct. 2, 2007 |
| 7251721 |
Conditional link pointer register sets marking the beginning and end of a conditional instruction block where each set corresponds to a single stage of a pipeline that moves link pointers thro |
Jul. 31, 2007 |
| 7216218 |
Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations |
May. 8, 2007 |
| 7184003 |
Personal electronics device with display switching |
Feb. 27, 2007 |
| 7130986 |
Determining if a register is ready to exchange data with a processing element |
Oct. 31, 2006 |
| 7111119 |
Device and method for performing information processing using plurality of processors |
Sep. 19, 2006 |
| 7065215 |
Microprocessor with program and data protection function under multi-task environment |
Jun. 20, 2006 |
| 7032098 |
Data-driven type information processing apparatus and information processing method allowing for effective use of memory |
Apr. 18, 2006 |
| 7028108 |
System and method for controlling data transfer for data array control unit having first and second selector with data shift register |
Apr. 11, 2006 |
| 7003648 |
Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU |
Feb. 21, 2006 |
| 6986029 |
Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein |
Jan. 10, 2006 |
| 6928457 |
Duplicated naming service in a distributed processing system |
Aug. 9, 2005 |
| 6922737 |
Storage control device and method for management of storage control device |
Jul. 26, 2005 |
| 6862676 |
Superscalar processor having content addressable memory structures for determining dependencies |
Mar. 1, 2005 |
| 6775760 |
Integrated circuit and recording medium on which data on integrated circuit is recorded |
Aug. 10, 2004 |
| 6775687 |
Exchanging supplemental information fields between a client and a server |
Aug. 10, 2004 |
| 6757817 |
Apparatus having a cache and a loop buffer |
Jun. 29, 2004 |
| 6728862 |
Processor array and parallel data processing methods |
Apr. 27, 2004 |
| 6711665 |
Associative processor |
Mar. 23, 2004 |
| 6654646 |
Enhanced memory addressing control |
Nov. 25, 2003 |
| 6643763 |
Register pipe for multi-processing engine environment |
Nov. 4, 2003 |
| 6629235 |
Condition code register architecture for supporting multiple execution units |
Sep. 30, 2003 |
| 6591354 |
Separate byte control on fully synchronous pipelined SRAM |
Jul. 8, 2003 |
| 6530012 |
Setting condition values in a computer |
Mar. 4, 2003 |
| 6526500 |
Data driven type information processing system consisting of interconnected data driven type information processing devices |
Feb. 25, 2003 |
| 6513101 |
Expiring host selected scratch logical volumes in an automated data storage library |
Jan. 28, 2003 |
| 6493818 |
Technique for pipelining synchronization to maintain throughput across two asynchronous clock domain boundaries |
Dec. 10, 2002 |
| 6470380 |
Signal processing device accessible as memory |
Oct. 22, 2002 |
| 6460131 |
FPGA input output buffer with registered tristate enable |
Oct. 1, 2002 |
| 6438677 |
Dynamic handling of object versions to support space and time dimensional program execution |
Aug. 20, 2002 |
| 6353881 |
Supporting space-time dimensional program execution by selectively versioning memory updates |
Mar. 5, 2002 |
| 6327622 |
Load balancing in a network environment |
Dec. 4, 2001 |
| 6195746 |
Dynamically typed register architecture |
Feb. 27, 2001 |
| 6189084 |
Debugging method and monitoring method for analysis instruments |
Feb. 13, 2001 |
| 6182204 |
PC card capable of providing multiple and/or different card information structures to a personal computer |
Jan. 30, 2001 |
| 6131152 |
Planar cache layout and instruction stream therefor |
Oct. 10, 2000 |
| 6098162 |
Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register |
Aug. 1, 2000 |
| 6092178 |
System for responding to a resource request |
Jul. 18, 2000 |
| 6088526 |
Scalable multiple level tab oriented interconnect architecture |
Jul. 11, 2000 |
| 6029239 |
Configuring a communications system with a configurable data transfer architecture |
Feb. 22, 2000 |
| 6023752 |
Digital data apparatus for transferring data between NTDS and bus topology data buses |
Feb. 8, 2000 |
| 5890006 |
Apparatus for extracting instruction specific bytes from an instruction |
Mar. 30, 1999 |
| 5872991 |
Data driven information processor for processing data packet including common identification information and plurality of pieces of data |
Feb. 16, 1999 |
| 5831871 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Nov. 3, 1998 |
| 5826098 |
Data processing system which converts received data packet into extended packet with prescribed field for accumulation process |
Oct. 20, 1998 |
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