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Class Information
Number: 712/26
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Data driven or demand driven processor > Detection/pairing based on destination, id tag, or data
Description: Subject matter which is directed to specific structure or operation to perform detecting or pairing dependent upon intended destination, a particular identification tag or data itself.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620694 |
Early issue of transaction ID |
Nov. 17, 2009 |
| 7555738 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Jun. 30, 2009 |
| 7546398 |
System and method for distributing virtual input/output operations across multiple logical partitions |
Jun. 9, 2009 |
| 7493469 |
Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium |
Feb. 17, 2009 |
| 7406653 |
Anomaly detection based on directional data |
Jul. 29, 2008 |
| 7398301 |
Method and apparatus for facilitating distributed delivery of content across a computer network |
Jul. 8, 2008 |
| 7376890 |
Method and system for checking rotate, shift and sign extension functions using a modulo function |
May. 20, 2008 |
| 7370182 |
Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor |
May. 6, 2008 |
| 7337443 |
Method and apparatus for processing program threads |
Feb. 26, 2008 |
| 7278013 |
Apparatus having a cache and a loop buffer |
Oct. 2, 2007 |
| 7266671 |
Register addressing |
Sep. 4, 2007 |
| 7237041 |
Systems and methods for automatic assignment of identification codes to devices |
Jun. 26, 2007 |
| 7188047 |
System and methods for providing histogram computation in a high precision rasterization data pipeline |
Mar. 6, 2007 |
| 7174525 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Feb. 6, 2007 |
| 7130986 |
Determining if a register is ready to exchange data with a processing element |
Oct. 31, 2006 |
| 7124280 |
Execution control apparatus of data driven information processor for instruction inputs |
Oct. 17, 2006 |
| 7100025 |
Apparatus and method for performing single-instruction multiple-data instructions |
Aug. 29, 2006 |
| 7089405 |
Index-based scoreboarding system and method |
Aug. 8, 2006 |
| 7032098 |
Data-driven type information processing apparatus and information processing method allowing for effective use of memory |
Apr. 18, 2006 |
| 7003648 |
Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU |
Feb. 21, 2006 |
| 6976150 |
Resource flow computing device |
Dec. 13, 2005 |
| 6954843 |
Data driven information processor capable of internally processing data in a constant frequency irrespective of an input frequency of a data packet from the outside |
Oct. 11, 2005 |
| 6904511 |
Method and apparatus for register file port reduction in a multithreaded processor |
Jun. 7, 2005 |
| 6792522 |
Data driven information processor carrying out processing using packet stored with plurality of operand data |
Sep. 14, 2004 |
| 6782521 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Aug. 24, 2004 |
| 6757817 |
Apparatus having a cache and a loop buffer |
Jun. 29, 2004 |
| 6754807 |
System and method for managing vertical dependencies in a digital signal processor |
Jun. 22, 2004 |
| 6711665 |
Associative processor |
Mar. 23, 2004 |
| 6625146 |
Method and apparatus for operating a network switch in a CPU-less environment |
Sep. 23, 2003 |
| 6598147 |
Data processing device and method |
Jul. 22, 2003 |
| 6526500 |
Data driven type information processing system consisting of interconnected data driven type information processing devices |
Feb. 25, 2003 |
| 6401232 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
Jun. 4, 2002 |
| 6310876 |
Method and apparatus for managing bin chains in a memory |
Oct. 30, 2001 |
| 6289435 |
Re-use of special purposed registers as general purpose registers |
Sep. 11, 2001 |
| 6282631 |
Programmable RISC-DSP architecture |
Aug. 28, 2001 |
| 6237086 |
1 Method to prevent pipeline stalls in superscalar stack based computing systems |
May. 22, 2001 |
| 6134645 |
Instruction completion logic distributed among execution units for improving completion efficiency |
Oct. 17, 2000 |
| 6088526 |
Scalable multiple level tab oriented interconnect architecture |
Jul. 11, 2000 |
| 6083274 |
Integrated structure layout and layout of interconnections for an integrated circuit chip |
Jul. 4, 2000 |
| 6061777 |
Apparatus and method for reducing the number of rename registers required in the operation of a processor |
May. 9, 2000 |
| 6032245 |
Method and system for interrupt handling in a multi-processor computer system executing speculative instruction threads |
Feb. 29, 2000 |
| 6029001 |
Method of compiling a computer program for performing parallel image processing |
Feb. 22, 2000 |
| 6026485 |
Instruction folding for a stack-based machine |
Feb. 15, 2000 |
| 5974260 |
Data processor to control a sequence of instructions to be executed by rearranging the instruction blocks |
Oct. 26, 1999 |
| 5937177 |
Control structure for a high-speed asynchronous pipeline |
Aug. 10, 1999 |
| 5919251 |
Search mechanism for a rotating pointer buffer |
Jul. 6, 1999 |
| 5872991 |
Data driven information processor for processing data packet including common identification information and plurality of pieces of data |
Feb. 16, 1999 |
| 5870620 |
Data driven type information processor with reduced instruction execution requirements |
Feb. 9, 1999 |
| 5870578 |
Workload balancing in a microprocessor for reduced instruction dispatch stalling |
Feb. 9, 1999 |
| 5860019 |
Data driven information processor having pipeline processing units connected in series including processing portions connected in parallel |
Jan. 12, 1999 |
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