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Class Information
Number: 712/25
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Data driven or demand driven processor
Description: Subject matter wherein a plural processor structure performs a calculation when all required data is present (data-driven) or when other processors request a calculation result (demand-driven).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7493469 |
Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium |
Feb. 17, 2009 |
| 7490218 |
Building a wavecache |
Feb. 10, 2009 |
| 7406685 |
System and method for whole-system program analysis |
Jul. 29, 2008 |
| 7383425 |
Massively reduced instruction set processor |
Jun. 3, 2008 |
| 7373481 |
Distributed-structure-based parallel module structure and parallel processing method |
May. 13, 2008 |
| 7340586 |
Data transfer for debugging in data driven type processor processing data packet with data flow program including transfer control bit setting instruction |
Mar. 4, 2008 |
| 7280539 |
Data driven type information processing apparatus |
Oct. 9, 2007 |
| 7237089 |
SIMD operation method and SIMD operation apparatus that implement SIMD operations without a large increase in the number of instructions |
Jun. 26, 2007 |
| 7130986 |
Determining if a register is ready to exchange data with a processing element |
Oct. 31, 2006 |
| 7127589 |
Data processor |
Oct. 24, 2006 |
| 7089407 |
Packet processing device processing input packet data in a packet routing device |
Aug. 8, 2006 |
| 7082515 |
Data driven type information processing apparatus having deadlock breaking function |
Jul. 25, 2006 |
| 7057763 |
Multi-mode print data processing |
Jun. 6, 2006 |
| 7035996 |
Generating data type token value error in stream computer |
Apr. 25, 2006 |
| 7028108 |
System and method for controlling data transfer for data array control unit having first and second selector with data shift register |
Apr. 11, 2006 |
| 7000098 |
Passing a received packet for modifying pipelining processing engines' routine instructions |
Feb. 14, 2006 |
| 7000022 |
Flow of streaming data through multiple processing modules |
Feb. 14, 2006 |
| 6993639 |
Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell |
Jan. 31, 2006 |
| 6959004 |
Data driven information processing apparatus |
Oct. 25, 2005 |
| 6954843 |
Data driven information processor capable of internally processing data in a constant frequency irrespective of an input frequency of a data packet from the outside |
Oct. 11, 2005 |
| 6941448 |
Data-driven processor having multiple-precision data processing function and data processing method thereof |
Sep. 6, 2005 |
| 6925549 |
Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages |
Aug. 2, 2005 |
| 6922736 |
Computer system and data processing method |
Jul. 26, 2005 |
| 6823443 |
Data driven type apparatus and method with router operating at a different transfer rate than system to attain higher throughput |
Nov. 23, 2004 |
| 6813703 |
Emulation system for data-driven processor |
Nov. 2, 2004 |
| 6792522 |
Data driven information processor carrying out processing using packet stored with plurality of operand data |
Sep. 14, 2004 |
| 6775788 |
Method for providing a synchronous communication and transaction between functions on an integrated circuit therefore the functions operate independently at their own optimized speeds |
Aug. 10, 2004 |
| 6766437 |
Composite uniprocessor |
Jul. 20, 2004 |
| 6760831 |
Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution |
Jul. 6, 2004 |
| 6748516 |
Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously |
Jun. 8, 2004 |
| 6732140 |
System and method for dynamic allocation of software resources |
May. 4, 2004 |
| 6715061 |
Multimedia-instruction acceleration device for increasing efficiency and method for the same |
Mar. 30, 2004 |
| 6708272 |
Information encryption system and method |
Mar. 16, 2004 |
| 6654646 |
Enhanced memory addressing control |
Nov. 25, 2003 |
| 6615341 |
Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control |
Sep. 2, 2003 |
| 6530011 |
Method and apparatus for vector register with scalar values |
Mar. 4, 2003 |
| 6526500 |
Data driven type information processing system consisting of interconnected data driven type information processing devices |
Feb. 25, 2003 |
| 6502180 |
Asynchronous circuits with pipelined completion process |
Dec. 31, 2002 |
| 6487617 |
Source-destination re-timed cooperative communication bus |
Nov. 26, 2002 |
| 6460131 |
FPGA input output buffer with registered tristate enable |
Oct. 1, 2002 |
| 6446034 |
Processor emulation virtual memory address translation |
Sep. 3, 2002 |
| 6397320 |
Method for just-in-time delivery of load data via cycle of dependency |
May. 28, 2002 |
| 6381692 |
Pipelined asynchronous processing |
Apr. 30, 2002 |
| 6339807 |
Multiprocessor system and the bus arbitrating method of the same |
Jan. 15, 2002 |
| 6275928 |
Microprocessor instruction pipeline having inhibit logic at each stage |
Aug. 14, 2001 |
| 6247115 |
Non-stalling circular counterflow pipeline processor with reorder buffer |
Jun. 12, 2001 |
| 6243800 |
Computer |
Jun. 5, 2001 |
| 6195628 |
Waveform manipulation in time warp simulation |
Feb. 27, 2001 |
| 6157995 |
Circuit and method for reducing data dependencies between instructions |
Dec. 5, 2000 |
| 6145073 |
Data flow integrated circuit architecture |
Nov. 7, 2000 |
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