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Class Information
Number: 712/245
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing control > Processing sequence control (i.e., microsequencing)
Description: Subject matter including means or steps for controlling a sequencing of an execution of a microinstruction.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7415602 |
Apparatus and method for processing a sequence of jump instructions |
Aug. 19, 2008 |
| 7412590 |
Information processing apparatus and context switching method |
Aug. 12, 2008 |
| 7404068 |
Single operation per-bit memory access |
Jul. 22, 2008 |
| 7401328 |
Software-implemented grouping techniques for use in a superscalar data processing system |
Jul. 15, 2008 |
| 7401211 |
Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor |
Jul. 15, 2008 |
| 7398376 |
Instructions for ordering execution in pipelined processes |
Jul. 8, 2008 |
| 7389407 |
Central control system and method for using state information to model inflight pipelined instructions |
Jun. 17, 2008 |
| 7386710 |
Methods and apparatus for scalable array processor interrupt detection and response |
Jun. 10, 2008 |
| 7376844 |
Countermeasure method for a microcontroller based on a pipeline architecture |
May. 20, 2008 |
| 7376818 |
Program translator and processor |
May. 20, 2008 |
| 7373490 |
Emptying packed data state during execution of packed data instructions |
May. 13, 2008 |
| 7370136 |
Efficient and flexible sequencing of data processing units extending VLIW architecture |
May. 6, 2008 |
| 7370181 |
Single stepping a virtual machine guest using a reorder buffer |
May. 6, 2008 |
| 7360062 |
Method and apparatus for selecting an instruction thread for processing in a multi-thread processor |
Apr. 15, 2008 |
| 7353337 |
Reducing cache effects of certain code pieces |
Apr. 1, 2008 |
| 7349398 |
Method and apparatus for out-of-order processing of packets |
Mar. 25, 2008 |
| 7349399 |
Method and apparatus for out-of-order processing of packets using linked lists |
Mar. 25, 2008 |
| 7308593 |
Interlocked synchronous pipeline clock gating |
Dec. 11, 2007 |
| 7305649 |
Automatic generation of a streaming processor circuit |
Dec. 4, 2007 |
| 7287146 |
Array-type computer processor |
Oct. 23, 2007 |
| 7278013 |
Apparatus having a cache and a loop buffer |
Oct. 2, 2007 |
| 7254689 |
Decompression of block-sorted data |
Aug. 7, 2007 |
| 7237100 |
Transaction redirection mechanism for handling late specification changes and design errors |
Jun. 26, 2007 |
| 7231261 |
Method for automatically obtaining an operational sequence of processes and a tool for performing such method |
Jun. 12, 2007 |
| 7231511 |
Microinstruction pointer stack including speculative pointers for out-of-order execution |
Jun. 12, 2007 |
| 7213136 |
Apparatus and method for redundant zero micro-operation removal |
May. 1, 2007 |
| 7213137 |
Allocation of processor bandwidth between main program and interrupt service instruction based on interrupt priority and retiring micro-ops to cache |
May. 1, 2007 |
| 7210129 |
Method for translating programs for reconfigurable architectures |
Apr. 24, 2007 |
| 7203935 |
Hardware/software platform for rapid prototyping of code compression technologies |
Apr. 10, 2007 |
| 7191321 |
Microengine for parallel processor architecture |
Mar. 13, 2007 |
| 7185177 |
Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors |
Feb. 27, 2007 |
| 7159099 |
Streaming vector processor with reconfigurable interconnection switch |
Jan. 2, 2007 |
| 7155718 |
Method and apparatus to suspend and resume on next instruction for a microcontroller |
Dec. 26, 2006 |
| 7149883 |
Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue |
Dec. 12, 2006 |
| 7127530 |
Command issuing apparatus for high-speed serial interface |
Oct. 24, 2006 |
| 7120903 |
Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus |
Oct. 10, 2006 |
| 7107361 |
Coupled computers and a method of coupling computers |
Sep. 12, 2006 |
| 7098921 |
Method, system and computer program product for efficiently utilizing limited resources in a graphics device |
Aug. 29, 2006 |
| 7100028 |
Multiple entry points for system call instructions |
Aug. 29, 2006 |
| 7080241 |
Mechanism for self-initiated instruction issuing and method therefor |
Jul. 18, 2006 |
| 7065665 |
Interlocked synchronous pipeline clock gating |
Jun. 20, 2006 |
| 7062762 |
Partitioning symmetric nodes efficiently in a split register file architecture |
Jun. 13, 2006 |
| 7058735 |
Method and apparatus for local and distributed data memory access ("DMA") control |
Jun. 6, 2006 |
| 7043729 |
Reducing interrupt latency while polling |
May. 9, 2006 |
| 7024538 |
Processor multiple function units executing cycle specifying variable length instruction block and using common target block address updated pointers |
Apr. 4, 2006 |
| 7016984 |
System controller using plural CPU's |
Mar. 21, 2006 |
| 7000097 |
System and method for handling load and/or store operations in a superscalar microprocessor |
Feb. 14, 2006 |
| 6996755 |
Squence control circuit |
Feb. 7, 2006 |
| 6986029 |
Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein |
Jan. 10, 2006 |
| 6965987 |
System and method for handling load and/or store operations in a superscalar microprocessor |
Nov. 15, 2005 |
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