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Class Information
Number: 712/244
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing control > Branching (e.g., delayed branch, loop control, branch predict, interrupt) > Exeception processing (e.g., interrupts and traps)
Description: Subject matter including means or steps for handling asynchronous or unexpected changes in instruction data flow.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7617389 |
Event notifying method, event notifying device and processor system permitting inconsistent state of a counter managing number of non-notified events |
Nov. 10, 2009 |
| 7613911 |
Prefetching exception vectors by early lookup exception vectors within a cache memory |
Nov. 3, 2009 |
| 7613912 |
System and method for simulating hardware interrupts |
Nov. 3, 2009 |
| 7613961 |
CPU register diagnostic testing |
Nov. 3, 2009 |
| 7610475 |
Programmable logic configuration for instruction extensions |
Oct. 27, 2009 |
| 7607042 |
Adjusting a processor operating parameter based on a performance criterion |
Oct. 20, 2009 |
| 7607133 |
Interrupt processing control |
Oct. 20, 2009 |
| 7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation |
Oct. 13, 2009 |
| 7600100 |
Instruction encoding for system register bit set and clear |
Oct. 6, 2009 |
| 7596779 |
Condition management callback system and method of operation thereof |
Sep. 29, 2009 |
| 7594103 |
Microprocessor and method of processing instructions for responding to interrupt condition |
Sep. 22, 2009 |
| 7581090 |
Interrupt control apparatus and method |
Aug. 25, 2009 |
| 7577962 |
Routing exceptions to operating system subsystems |
Aug. 18, 2009 |
| 7577961 |
Methods and apparatus for exception-based programming |
Aug. 18, 2009 |
| 7577954 |
Process management method and image forming apparatus |
Aug. 18, 2009 |
| 7555703 |
Method and apparatus for reducing false error detection in a microprocessor |
Jun. 30, 2009 |
| 7546446 |
Selective interrupt suppression |
Jun. 9, 2009 |
| 7539853 |
Handling interrupts in data processing of data in which only a portion of a function has been processed |
May. 26, 2009 |
| 7529917 |
Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array |
May. 5, 2009 |
| 7523296 |
System and method for handling exceptions and branch mispredictions in a superscalar microprocessor |
Apr. 21, 2009 |
| 7522516 |
Exception handling system for packet processing system |
Apr. 21, 2009 |
| 7516453 |
Binary translator with precise exception synchronization mechanism |
Apr. 7, 2009 |
| 7506207 |
Method and system using hardware assistance for continuance of trap mode during or after interruption sequences |
Mar. 17, 2009 |
| 7502917 |
High speed memory cloning facility via a lockless multiprocessor mechanism |
Mar. 10, 2009 |
| 7496896 |
Accessing return values and exceptions |
Feb. 24, 2009 |
| 7487341 |
Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource |
Feb. 3, 2009 |
| 7475232 |
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines |
Jan. 6, 2009 |
| 7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor |
Dec. 30, 2008 |
| 7461386 |
Zero overhead exception handling |
Dec. 2, 2008 |
| 7451296 |
Method and apparatus for pausing execution in a processor or the like |
Nov. 11, 2008 |
| 7451298 |
Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode |
Nov. 11, 2008 |
| 7451300 |
Explicit control of speculation |
Nov. 11, 2008 |
| 7447732 |
Recoverable return code tracking and notification for autonomic systems |
Nov. 4, 2008 |
| 7444500 |
Method for executing a 32-bit flat address program during a system management mode interrupt |
Oct. 28, 2008 |
| 7437542 |
Identifying and processing essential and non-essential code separately |
Oct. 14, 2008 |
| 7434035 |
Method and system for processing instructions in grouped and non-grouped modes |
Oct. 7, 2008 |
| 7434038 |
Microprocessor arrangement for updating flag bits for security purposes and method for operating the same |
Oct. 7, 2008 |
| 7434039 |
Computer processor capable of responding with comparable efficiency to both software-state-independent and state-dependent events |
Oct. 7, 2008 |
| 7426630 |
Arbitration of window swap operations |
Sep. 16, 2008 |
| 7418584 |
Executing system management mode code as virtual machine guest |
Aug. 26, 2008 |
| 7418585 |
Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts |
Aug. 26, 2008 |
| 7401211 |
Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor |
Jul. 15, 2008 |
| 7398371 |
Shared translation look-aside buffer and method |
Jul. 8, 2008 |
| 7398372 |
Fusing load and alu operations |
Jul. 8, 2008 |
| 7398378 |
Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors |
Jul. 8, 2008 |
| 7389407 |
Central control system and method for using state information to model inflight pipelined instructions |
Jun. 17, 2008 |
| 7389496 |
Condition management system and a method of operation thereof |
Jun. 17, 2008 |
| 7386710 |
Methods and apparatus for scalable array processor interrupt detection and response |
Jun. 10, 2008 |
| 7386647 |
System and method for processing an interrupt in a processor supporting multithread execution |
Jun. 10, 2008 |
| 7383587 |
Exception handling control in a secure processing system |
Jun. 3, 2008 |
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