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Class Information
Number: 712/241
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing control > Branching (e.g., delayed branch, loop control, branch predict, interrupt) > Loop execution
Description: Subject matter including means or steps for controlling an execution of a program loop.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7434031 |
Execution displacement read-write alias prediction |
Oct. 7, 2008 |
| 7428632 |
Branch prediction mechanism using a branch cache memory and an extended pattern cache |
Sep. 23, 2008 |
| 7406590 |
Methods and apparatus for early loop bottom detection in digital signal processors |
Jul. 29, 2008 |
| 7401205 |
High performance RISC instruction set digital signal processor having circular buffer and looping controls |
Jul. 15, 2008 |
| 7395531 |
Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements |
Jul. 1, 2008 |
| 7395419 |
Macroscalar processor architecture |
Jul. 1, 2008 |
| 7380112 |
Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags |
May. 27, 2008 |
| 7370136 |
Efficient and flexible sequencing of data processing units extending VLIW architecture |
May. 6, 2008 |
| 7366885 |
Method for optimizing loop control of microcoded instructions |
Apr. 29, 2008 |
| 7346763 |
Processor instruction with repeated execution code |
Mar. 18, 2008 |
| 7330964 |
Microprocessor with independent SIMD loop buffer |
Feb. 12, 2008 |
| 7328329 |
Controlling processing of data stream elements using a set of specific function units |
Feb. 5, 2008 |
| 7302557 |
Method and apparatus for modulo scheduled loop execution in a processor architecture |
Nov. 27, 2007 |
| 7290123 |
System, device and method of maintaining in an array loop iteration data related to branch entries of a loop detector |
Oct. 30, 2007 |
| 7278013 |
Apparatus having a cache and a loop buffer |
Oct. 2, 2007 |
| 7272704 |
Hardware looping mechanism and method for efficient execution of discontinuity instructions |
Sep. 18, 2007 |
| 7249248 |
Method, apparatus, and system for variable increment multi-index looping operations |
Jul. 24, 2007 |
| 7237229 |
Debugging aid parallel execution of a plurality of iterations with source lists display corresponding to each iteration |
Jun. 26, 2007 |
| 7206927 |
Pipelined processor method and circuit with interleaving of iterative operations |
Apr. 17, 2007 |
| 7194610 |
Processor and pipeline reconfiguration control method |
Mar. 20, 2007 |
| 7178013 |
Repeat function for processing of repetitive instruction streams |
Feb. 13, 2007 |
| 7171544 |
Run-time parallelization of loops in computer programs by access patterns |
Jan. 30, 2007 |
| 7165254 |
Thread switch upon spin loop detection by threshold count of spin lock reading load instruction |
Jan. 16, 2007 |
| 7162620 |
Methods and apparatus for multi-processing execution of computer instructions |
Jan. 9, 2007 |
| 7159103 |
Zero-overhead loop operation in microprocessor having instruction buffer |
Jan. 2, 2007 |
| 7136989 |
Parallel computation processor, parallel computation control method and program thereof |
Nov. 14, 2006 |
| 7136992 |
Method and apparatus for a stew-based loop predictor |
Nov. 14, 2006 |
| 7130991 |
Method and apparatus for loop detection utilizing multiple loop counters and a branch promotion scheme |
Oct. 31, 2006 |
| 7120907 |
Unrolling loops with partial hot traces |
Oct. 10, 2006 |
| 7100156 |
Interprocedural dead store elimination |
Aug. 29, 2006 |
| 7093112 |
Method and apparatus for caching short program loops within an instruction FIFO |
Aug. 15, 2006 |
| 7085916 |
Efficient instruction prefetch mechanism employing selective validity of cached instructions for digital signal processor and method of operation thereof |
Aug. 1, 2006 |
| 7080240 |
Data processing apparatus |
Jul. 18, 2006 |
| 7080239 |
Loop control circuit and loop control method |
Jul. 18, 2006 |
| 7065636 |
Hardware loops and pipeline system using advanced generation of loop parameters |
Jun. 20, 2006 |
| 7062684 |
Enabling tracing of a repeat instruction |
Jun. 13, 2006 |
| 7058938 |
Method and system for scheduling software pipelined loops |
Jun. 6, 2006 |
| 7039793 |
Microprocessor apparatus and method for accelerating execution of repeat string instructions |
May. 2, 2006 |
| 7028168 |
System and method for performing matrix operations |
Apr. 11, 2006 |
| 7020749 |
Signal processor, prefetch instruction method and prefetch instruction program |
Mar. 28, 2006 |
| 7020769 |
Method and system for processing a loop of instructions |
Mar. 28, 2006 |
| 7010676 |
Last iteration loop branch prediction upon counter threshold and resolution upon counter one |
Mar. 7, 2006 |
| 7010677 |
Data processor speeding up repeat processing by inhibiting remaining instructions after a break in a repeat block |
Mar. 7, 2006 |
| 6990571 |
Method for memory optimization in a digital signal processor |
Jan. 24, 2006 |
| 6990570 |
Processor with a computer repeat instruction |
Jan. 24, 2006 |
| 6988190 |
Method of an address trace cache storing loop control information to conserve trace cache area |
Jan. 17, 2006 |
| 6986028 |
Repeat block with zero cycle overhead nesting |
Jan. 10, 2006 |
| 6986131 |
Method and apparatus for efficient code generation for modulo scheduled uncounted loops |
Jan. 10, 2006 |
| 6976158 |
Repeat instruction with interrupt |
Dec. 13, 2005 |
| 6968448 |
Microsequencer with nested loop counters |
Nov. 22, 2005 |
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