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Class Information
Number: 712/24
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Long instruction word
Description: Subject matter comprising an architecture which includes compiler scheduled issuing of multiple opcodes per instruction.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7590824 |
Mixed superscalar and VLIW instruction issuing and processing method and system |
Sep. 15, 2009 |
| 7584405 |
Fault-detecting computer system |
Sep. 1, 2009 |
| 7574583 |
Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor |
Aug. 11, 2009 |
| 7533243 |
Processor for executing highly efficient VLIW |
May. 12, 2009 |
| 7533244 |
Network-on-chip dataflow architecture |
May. 12, 2009 |
| 7506137 |
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions |
Mar. 17, 2009 |
| 7496656 |
Processing instruction words |
Feb. 24, 2009 |
| 7484075 |
Method and apparatus for providing fast remote register access in a clustered VLIW processor using partitioned register files |
Jan. 27, 2009 |
| 7475222 |
Multi-threaded processor having compound instruction and operation formats |
Jan. 6, 2009 |
| 7472257 |
Rerouting VLIW instructions to accommodate execution units deactivated upon detection by dispatch units of dedicated instruction alerting multiple successive removed NOPs |
Dec. 30, 2008 |
| 7444276 |
Hardware acceleration system for logic simulation using shift register as local cache |
Oct. 28, 2008 |
| 7437534 |
Local and global register partitioning technique |
Oct. 14, 2008 |
| 7424594 |
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture |
Sep. 9, 2008 |
| 7418575 |
Long instruction word processing with instruction extensions |
Aug. 26, 2008 |
| 7412591 |
Apparatus and method for switchable conditional execution in a VLIW processor |
Aug. 12, 2008 |
| 7409530 |
Method and apparatus for compressing VLIW instruction and sharing subinstructions |
Aug. 5, 2008 |
| 7401204 |
Parallel Processor efficiently executing variable instruction word |
Jul. 15, 2008 |
| 7398372 |
Fusing load and alu operations |
Jul. 8, 2008 |
| 7395408 |
Parallel execution processor and instruction assigning making use of group number in processing elements |
Jul. 1, 2008 |
| 7383422 |
Very long instruction word (VLIW) computer having an efficient instruction code format |
Jun. 3, 2008 |
| 7380100 |
Data processing system and control method utilizing a plurality of date transfer means |
May. 27, 2008 |
| 7376813 |
Register move instruction for section select of source operand |
May. 20, 2008 |
| 7376812 |
Vector co-processor for configurable and extensible processor architecture |
May. 20, 2008 |
| 7370136 |
Efficient and flexible sequencing of data processing units extending VLIW architecture |
May. 6, 2008 |
| 7370182 |
Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor |
May. 6, 2008 |
| 7366874 |
Apparatus and method for dispatching very long instruction word having variable length |
Apr. 29, 2008 |
| 7343475 |
Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction |
Mar. 11, 2008 |
| 7343471 |
Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assi |
Mar. 11, 2008 |
| 7340591 |
Providing parallel operand functions using register file and extra path storage |
Mar. 4, 2008 |
| 7325232 |
Compiler for multiple processor and distributed memory architectures |
Jan. 29, 2008 |
| 7313646 |
Interfacing of functional modules in an on-chip system |
Dec. 25, 2007 |
| 7313671 |
Processing apparatus, processing method and compiler |
Dec. 25, 2007 |
| 7310723 |
Methods and systems employing a flag for deferring exception handling to a commit or rollback point |
Dec. 18, 2007 |
| 7305542 |
Instruction length decoder |
Dec. 4, 2007 |
| 7302555 |
Zero overhead branching and looping in time stationary processors |
Nov. 27, 2007 |
| 7302552 |
System for processing VLIW words containing variable length instructions having embedded instruction length identifiers |
Nov. 27, 2007 |
| 7299339 |
Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework |
Nov. 20, 2007 |
| 7296120 |
Mechanism that provides efficient multi-word load atomicity |
Nov. 13, 2007 |
| 7290122 |
Dataflow graph compression for power reduction in a vector processor |
Oct. 30, 2007 |
| 7290120 |
Microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer |
Oct. 30, 2007 |
| 7287151 |
Communication path to each part of distributed register file from functional units in addition to partial communication network |
Oct. 23, 2007 |
| 7281117 |
Processor executing SIMD instructions |
Oct. 9, 2007 |
| 7281119 |
Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes |
Oct. 9, 2007 |
| 7269720 |
Dynamically controlling execution of operations within a multi-operation instruction |
Sep. 11, 2007 |
| 7266671 |
Register addressing |
Sep. 4, 2007 |
| 7260709 |
Processing method and apparatus for implementing systolic arrays |
Aug. 21, 2007 |
| 7257696 |
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions |
Aug. 14, 2007 |
| 7254697 |
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch |
Aug. 7, 2007 |
| 7243213 |
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product |
Jul. 10, 2007 |
| 7234042 |
Identification bit at a predetermined instruction location that indicates whether the instruction is one or two independent operations and indicates the nature the operations executing in two |
Jun. 19, 2007 |
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