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Class Information
Number: 712/24
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Long instruction word
Description: Subject matter comprising an architecture which includes compiler scheduled issuing of multiple opcodes per instruction.

Patents under this class:
1 2 3 4 5 6 7

Patent Number Title Of Patent Date Issued
8713286 Register files for a digital signal processor operating in an interleaved multi-threaded environment Apr. 29, 2014
8707012 Implementing vector memory operations Apr. 22, 2014
8707013 On-demand predicate registers Apr. 22, 2014
8671266 Staging register file for use with multi-stage execution units Mar. 11, 2014
8656141 Architecture and programming in a parallel processing environment with switch-interconnected processors Feb. 18, 2014
8601244 Apparatus and method for generating VLIW, and processor and method for processing VLIW Dec. 3, 2013
8583895 Compressed instruction format for use in a VLIW processor Nov. 12, 2013
8516224 Pipeline replay support for multicycle operations Aug. 20, 2013
8510539 Spilling method involving register files based on communication costs and use ratio Aug. 13, 2013
8447961 Mechanism for efficient implementation of software pipelined loops in VLIW processors May. 21, 2013
8433553 Method and apparatus for designing a processor Apr. 30, 2013
8397000 System core for transferring data between an external device and memory Mar. 12, 2013
8364935 Data processing apparatus address range dependent parallelization of instructions Jan. 29, 2013
8316216 Implementing vector memory operations Nov. 20, 2012
8296479 System core for transferring data between an external device and memory Oct. 23, 2012
8250340 Processor for executing highly efficient VLIW Aug. 21, 2012
8191085 Method and apparatus for loading or storing multiple registers in a data processing system May. 29, 2012
8145888 Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit Mar. 27, 2012
8127115 Group formation with multiple taken branches per group Feb. 28, 2012
8117423 Pipeline replay support for multicycle operations Feb. 14, 2012
8117357 System core for transferring data between an external device and memory Feb. 14, 2012
8108658 Data processing circuit wherein functional units share read ports Jan. 31, 2012
8095775 Instruction pointers in very long instruction words Jan. 10, 2012
8069335 Processing system and method for executing instructions Nov. 29, 2011
8046568 Microprocessor with integrated high speed memory Oct. 25, 2011
8019971 Processor for executing highly efficient VLIW Sep. 13, 2011
8015391 Simultaneous multiple thread processor increasing number of instructions issued for thread detected to be processing loop Sep. 6, 2011
7971197 Automatic instruction set architecture generation Jun. 28, 2011
7962719 Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Jun. 14, 2011
7895413 Microprocessor including register renaming unit for renaming target registers in an instruction with physical registers in a register sub-file Feb. 22, 2011
7886135 Pipeline replay support for unaligned memory operations Feb. 8, 2011
7873794 Mechanism that provides efficient multi-word load atomicity Jan. 18, 2011
7861061 Processor instruction including option bits encoding which instructions of an instruction packet to execute Dec. 28, 2010
7831804 Multidimensional processor architecture Nov. 9, 2010
RE41703 Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication Sep. 14, 2010
7774581 Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same Aug. 10, 2010
7747843 Microprocessor with integrated high speed memory Jun. 29, 2010
7739479 Method for providing physics simulation data Jun. 15, 2010
7694301 Method and system for supporting input/output for a virtual machine Apr. 6, 2010
7685403 Pipeline replay support for multi-cycle operations Mar. 23, 2010
7681046 System with secure cryptographic capabilities using a hardware specific digital secret Mar. 16, 2010
7673119 VLIW optional fetch packet header extends instruction set space Mar. 2, 2010
7669041 Instruction-parallel processor with zero-performance-overhead operand copy Feb. 23, 2010
7664929 Data processing apparatus with parallel operating functional units Feb. 16, 2010
7647473 Instruction processing method for verifying basic instruction arrangement in VLIW instruction for variable length VLIW processor Jan. 12, 2010
7647474 Saving system context in the event of power loss Jan. 12, 2010
7640417 Instruction length decoder Dec. 29, 2009
7627735 Implementing vector memory operations Dec. 1, 2009
RE41012 Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor Nov. 24, 2009
7590824 Mixed superscalar and VLIW instruction issuing and processing method and system Sep. 15, 2009

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