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Class Information
Number: 712/23
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Superscalar
Description: Subject matter comprising an architecture which determines a group of upcoming instructions which do not mutually interfere with each other and issues or dispatches this group simultaneously.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8649508 System and method for implementing elliptic curve scalar multiplication in cryptography Feb. 11, 2014
8645714 Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions Feb. 4, 2014
8566570 Distributed multi-core memory initialization Oct. 22, 2013
8516223 Dispatching instruction from reservation station to vacant instruction queue of alternate arithmetic unit Aug. 20, 2013
8468540 Interrupt and exception handling for multi-streaming digital processors Jun. 18, 2013
8464089 Tracing apparatus and tracing system Jun. 11, 2013
8402256 Processing prefix code in instruction queue storing fetched sets of plural instructions in superscalar processor Mar. 19, 2013
8307198 Distributed multi-core memory initialization Nov. 6, 2012
8261085 Methods, apparatus and systems to improve security in computer systems Sep. 4, 2012
8250395 Dynamic voltage and frequency scaling (DVFS) control for simultaneous multi-threading (SMT) processors Aug. 21, 2012
8245015 Processor monitoring execution of a synchronization instruction issued to execution sections to detect completion of execution of preceding instructions in an identified thread Aug. 14, 2012
8219784 Assigning and pre-decoding group ID and tag ID prior to dispatching instructions in out-of-order processor Jul. 10, 2012
8200950 Sharing pipeline by inserting NOP to accommodate memory access request received from other processors Jun. 12, 2012
8195759 Performing externally assisted calls in a heterogeneous processing complex Jun. 5, 2012
8179540 Image forming apparatus and management system utilizing counter and job log information for usage tracking May. 15, 2012
8140831 Routing instructions in a processor Mar. 20, 2012
8074052 System and method for assigning tags to control instruction processing in a superscalar processor Dec. 6, 2011
8074060 Out-of-order execution microprocessor that selectively initiates instruction retirement early Dec. 6, 2011
8068109 Processor task and data management Nov. 29, 2011
8019975 System and method for handling load and/or store operations in a superscalar microprocessor Sep. 13, 2011
7966478 Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers Jun. 21, 2011
7941636 RISC microprocessor architecture implementing multiple typed register sets May. 10, 2011
7941635 High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution May. 10, 2011
7926062 Interrupt and exception handling for multi-streaming digital processors Apr. 12, 2011
7900207 Interrupt and exception handling for multi-streaming digital processors Mar. 1, 2011
7844797 System and method for handling load and/or store operations in a superscalar microprocessor Nov. 30, 2010
7840788 Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register Nov. 23, 2010
7822881 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like) Oct. 26, 2010
7802074 Superscalar RISC instruction scheduling Sep. 21, 2010
7739482 High-performance, superscalar-based computer system with out-of-order instruction execution Jun. 15, 2010
7734827 Operation of cell processors Jun. 8, 2010
7734897 Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads Jun. 8, 2010
7711934 Processor core and method for managing branch misprediction in an out-of-order processor pipeline May. 4, 2010
7712080 Systems and methods for parallel distributed programming May. 4, 2010
RE41293 Multiprocessor computer having configurable hardware system domains Apr. 27, 2010
7694112 Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation Apr. 6, 2010
7685402 RISC microprocessor architecture implementing multiple typed register sets Mar. 23, 2010
7664935 System and method for translating non-native instructions to native instructions for processing on a host processor Feb. 16, 2010
7653804 Resource sharing in multiple parallel pipelines Jan. 26, 2010
7590824 Mixed superscalar and VLIW instruction issuing and processing method and system Sep. 15, 2009
7562206 Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions Jul. 14, 2009
7555631 RISC microprocessor architecture implementing multiple typed register sets Jun. 30, 2009
7555632 High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Jun. 30, 2009
7533248 Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor May. 12, 2009
7506185 Selective power-down for high performance CPU/system Mar. 17, 2009
7490225 Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number Feb. 10, 2009
7467286 Executing partial-width packed data instructions Dec. 16, 2008
7467385 Interrupt and exception handling for multi-streaming digital processors Dec. 16, 2008
7464242 Method of load/store dependencies detection with dynamically changing address length Dec. 9, 2008
7460989 Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language Dec. 2, 2008

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