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Class Information
Number: 712/23
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Superscalar
Description: Subject matter comprising an architecture which determines a group of upcoming instructions which do not mutually interfere with each other and issues or dispatches this group simultaneously.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7590824 |
Mixed superscalar and VLIW instruction issuing and processing method and system |
Sep. 15, 2009 |
| 7562206 |
Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions |
Jul. 14, 2009 |
| 7555631 |
RISC microprocessor architecture implementing multiple typed register sets |
Jun. 30, 2009 |
| 7555632 |
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution |
Jun. 30, 2009 |
| 7533248 |
Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor |
May. 12, 2009 |
| 7506185 |
Selective power-down for high performance CPU/system |
Mar. 17, 2009 |
| 7490225 |
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number |
Feb. 10, 2009 |
| 7467385 |
Interrupt and exception handling for multi-streaming digital processors |
Dec. 16, 2008 |
| 7467286 |
Executing partial-width packed data instructions |
Dec. 16, 2008 |
| 7464242 |
Method of load/store dependencies detection with dynamically changing address length |
Dec. 9, 2008 |
| 7460989 |
Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language |
Dec. 2, 2008 |
| 7447876 |
System and method for handling load and/or store operations in a superscalar microprocessor |
Nov. 4, 2008 |
| 7430651 |
System and method for assigning tags to control instruction processing in a superscalar processor |
Sep. 30, 2008 |
| 7409670 |
Scheduling logic on a programmable device implemented using a high-level language |
Aug. 5, 2008 |
| 7401328 |
Software-implemented grouping techniques for use in a superscalar data processing system |
Jul. 15, 2008 |
| 7398375 |
Technique for reduced-tag dynamic scheduling and reduced-tag prediction |
Jul. 8, 2008 |
| 7392369 |
Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check |
Jun. 24, 2008 |
| 7376812 |
Vector co-processor for configurable and extensible processor architecture |
May. 20, 2008 |
| 7373481 |
Distributed-structure-based parallel module structure and parallel processing method |
May. 13, 2008 |
| 7373485 |
Clustered superscalar processor with communication control between clusters |
May. 13, 2008 |
| 7343473 |
System and method for translating non-native instructions to native instructions for processing on a host processor |
Mar. 11, 2008 |
| 7330963 |
Resolving all previous potentially excepting architectural operations before issuing store architectural operation |
Feb. 12, 2008 |
| 7318145 |
Random slip generator |
Jan. 8, 2008 |
| 7308559 |
Digital signal processor with cascaded SIMD organization |
Dec. 11, 2007 |
| 7281119 |
Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes |
Oct. 9, 2007 |
| 7254693 |
Selectively prohibiting speculative execution of conditional branch type based on instruction bit |
Aug. 7, 2007 |
| 7249243 |
Control word prediction and varying recovery upon comparing actual to set of stored words |
Jul. 24, 2007 |
| 7225320 |
Control architecture for a high-throughput multi-processor channel decoding system |
May. 29, 2007 |
| 7210024 |
Conditional instruction execution via emissary instruction for condition evaluation |
Apr. 24, 2007 |
| 7200737 |
Processor with a replay system that includes a replay queue for improved throughput |
Apr. 3, 2007 |
| 7171541 |
Register renaming system |
Jan. 30, 2007 |
| 7162610 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
Jan. 9, 2007 |
| 7143401 |
Single-chip multiprocessor with cycle-precise program scheduling of parallel execution |
Nov. 28, 2006 |
| 7136989 |
Parallel computation processor, parallel computation control method and program thereof |
Nov. 14, 2006 |
| 7111152 |
Computer system that operates in VLIW and superscalar modes and has selectable dependency control |
Sep. 19, 2006 |
| 7096347 |
Processor and method of testing a processor for hardware faults utilizing a pipeline interlocking test instruction |
Aug. 22, 2006 |
| 7089404 |
Method and apparatus for enhancing scheduling in an advanced microprocessor |
Aug. 8, 2006 |
| 7062636 |
Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation |
Jun. 13, 2006 |
| 7058795 |
Method and apparatus of branch prediction |
Jun. 6, 2006 |
| 7051187 |
Superscalar RISC instruction scheduling |
May. 23, 2006 |
| 7043624 |
System and method for assigning tags to control instruction processing in a superscalar processor |
May. 9, 2006 |
| 7028161 |
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution |
Apr. 11, 2006 |
| 7024542 |
System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions |
Apr. 4, 2006 |
| 7020879 |
Interrupt and exception handling for multi-streaming digital processors |
Mar. 28, 2006 |
| 7000097 |
System and method for handling load and/or store operations in a superscalar microprocessor |
Feb. 14, 2006 |
| 7000135 |
Clock control method and information processing device employing the clock control method |
Feb. 14, 2006 |
| 6996698 |
Blocking processing restrictions based on addresses |
Feb. 7, 2006 |
| 6978460 |
Processor having priority changing function according to threads |
Dec. 20, 2005 |
| 6965987 |
System and method for handling load and/or store operations in a superscalar microprocessor |
Nov. 15, 2005 |
| 6959375 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
Oct. 25, 2005 |
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