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Class Information
Number: 712/229
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing control > Mode switch or change
Description: Subject matter including means or steps for changing a mode of processing an instruction (e.g., sequential processing to parallel processing, etc.).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7434029 |
Inter-processor control |
Oct. 7, 2008 |
| 7430678 |
Low power operation control unit and program optimizing method |
Sep. 30, 2008 |
| 7421571 |
Apparatus and method for switching threads in multi-threading processors |
Sep. 2, 2008 |
| 7418584 |
Executing system management mode code as virtual machine guest |
Aug. 26, 2008 |
| 7418582 |
Versatile register file design for a multi-threaded processor utilizing different modes and register windows |
Aug. 26, 2008 |
| 7415383 |
Compiling method, apparatus, and program |
Aug. 19, 2008 |
| 7412591 |
Apparatus and method for switchable conditional execution in a VLIW processor |
Aug. 12, 2008 |
| 7406573 |
Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements |
Jul. 29, 2008 |
| 7395416 |
Computer processing system employing an instruction reorder buffer |
Jul. 1, 2008 |
| 7395418 |
Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread |
Jul. 1, 2008 |
| 7376819 |
Data processor with selectable word length |
May. 20, 2008 |
| 7363476 |
Method and apparatus to support an expanded register set |
Apr. 22, 2008 |
| 7360013 |
Method of rewriting flash EEPROM and electronic control device using same |
Apr. 15, 2008 |
| 7356670 |
Data processing system |
Apr. 8, 2008 |
| 7356647 |
Cache with integrated capability to write out entire cache |
Apr. 8, 2008 |
| 7353368 |
Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support |
Apr. 1, 2008 |
| 7350060 |
Method and apparatus for sending thread-execution-state-sensitive supervisory commands to a simultaneous multi-threaded (SMT) processor |
Mar. 25, 2008 |
| 7350035 |
Information-processing apparatus and electronic equipment using thereof |
Mar. 25, 2008 |
| 7343480 |
Single cycle context switching by swapping a primary latch value and a selected secondary latch value in a register file |
Mar. 11, 2008 |
| 7343602 |
Software controlled pre-execution in a multithreaded processor |
Mar. 11, 2008 |
| 7340313 |
Monitoring device for monitoring internal signals during initialization of an electronic circuit |
Mar. 4, 2008 |
| 7340643 |
Replay mechanism for correcting soft errors |
Mar. 4, 2008 |
| 7328329 |
Controlling processing of data stream elements using a set of specific function units |
Feb. 5, 2008 |
| 7321965 |
Integrated mechanism for suspension and deallocation of computational threads of execution in a processor |
Jan. 22, 2008 |
| 7318171 |
Policy-based response to system errors occurring during OS runtime |
Jan. 8, 2008 |
| 7290261 |
Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor |
Oct. 30, 2007 |
| 7281123 |
Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset |
Oct. 9, 2007 |
| 7281240 |
Mechanism for lossless, lock-free buffer switching in an arbitrary-context tracing framework |
Oct. 9, 2007 |
| 7260702 |
Systems and methods for running a legacy 32-bit x86 virtual machine on a 64-bit x86 processor |
Aug. 21, 2007 |
| 7249247 |
Common feature mode for microprocessors in a multiple microprocessor system |
Jul. 24, 2007 |
| 7243350 |
Speculative execution for java hardware accelerator |
Jul. 10, 2007 |
| 7237088 |
Methods and apparatus for providing context switching between software tasks with reconfigurable control |
Jun. 26, 2007 |
| 7237216 |
Clock gating approach to accommodate infrequent additional processing latencies |
Jun. 26, 2007 |
| 7218562 |
Recovering bit lines in a memory array after stopped clock operation |
May. 15, 2007 |
| 7213134 |
Using thread urgency in determining switch events in a temporal multithreaded processor unit |
May. 1, 2007 |
| 7203823 |
Partial and start-over threads in embedded real-time kernel |
Apr. 10, 2007 |
| 7197627 |
Multiple processor arrangement for conserving power |
Mar. 27, 2007 |
| 7191320 |
Apparatus and method for performing a detached load operation in a pipeline microprocessor |
Mar. 13, 2007 |
| 7181599 |
Method and apparatus for autonomic detection of cache "chase tail" conditions and storage of instructions/data in "chase tail" data structure |
Feb. 20, 2007 |
| 7181600 |
Read-only access to CPO registers |
Feb. 20, 2007 |
| 7174443 |
Run-time reconfiguration method for programmable units |
Feb. 6, 2007 |
| 7168065 |
Method for monitoring program flow to verify execution of proper instructions by a processor |
Jan. 23, 2007 |
| 7165257 |
Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts |
Jan. 16, 2007 |
| 7162617 |
Data processor with changeable architecture |
Jan. 9, 2007 |
| 7159099 |
Streaming vector processor with reconfigurable interconnection switch |
Jan. 2, 2007 |
| 7155600 |
Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor |
Dec. 26, 2006 |
| 7155721 |
Method and apparatus for communicating information between lock stepped processors |
Dec. 26, 2006 |
| 7155726 |
System for dynamic registration of privileged mode hooks in a device |
Dec. 26, 2006 |
| 7149878 |
Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values |
Dec. 12, 2006 |
| 7149882 |
Processor with instructions that operate on different data types stored in the same single logical register file |
Dec. 12, 2006 |
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