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Class Information
Number: 712/225
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing control > Processing control for data transfer
Description: Subject matter including means or steps for processing instruction data that specifically support or perform a data transfer operation.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7624251 |
Instructions for efficiently accessing unaligned partial vectors |
Nov. 24, 2009 |
| 7620797 |
Instructions for efficiently accessing unaligned vectors |
Nov. 17, 2009 |
| 7617386 |
Scheduling thread upon ready signal set when port transfers data on trigger time activation |
Nov. 10, 2009 |
| 7613909 |
Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor |
Nov. 3, 2009 |
| 7606998 |
Store instruction ordering for multi-core processor |
Oct. 20, 2009 |
| 7606974 |
Automatic caching generation in network applications |
Oct. 20, 2009 |
| 7594060 |
Data buffer allocation in a non-blocking data services platform using input/output switching fabric |
Sep. 22, 2009 |
| 7594101 |
Secure digital processing unit and method for protecting programs |
Sep. 22, 2009 |
| 7594100 |
Efficient store queue architecture |
Sep. 22, 2009 |
| 7594250 |
Method and system of program transmission optimization using a redundant transmission sequence |
Sep. 22, 2009 |
| 7587577 |
Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content |
Sep. 8, 2009 |
| 7583663 |
Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath |
Sep. 1, 2009 |
| 7577105 |
Cooperation information managing apparatus and gateway apparatus for use in cooperation information managing system |
Aug. 18, 2009 |
| 7568087 |
Partial load/store forward prediction |
Jul. 28, 2009 |
| 7565510 |
Microprocessor with a register selectively storing unaligned load instructions and control method thereof |
Jul. 21, 2009 |
| 7555637 |
Multi-port read/write operations based on register bits set for indicating select ports and transfer directions |
Jun. 30, 2009 |
| 7552247 |
Increased computer peripheral throughput by using data available withholding |
Jun. 23, 2009 |
| 7546441 |
Coprocessor interface controller |
Jun. 9, 2009 |
| 7543287 |
Using a block device interface to invoke device controller functionality |
Jun. 2, 2009 |
| 7539844 |
Prefetching indirect array accesses |
May. 26, 2009 |
| 7533238 |
Method for limiting the size of a local storage of a processor |
May. 12, 2009 |
| 7525457 |
Transforming design objects in a computer by converting data sets between data set types |
Apr. 28, 2009 |
| 7523449 |
System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture |
Apr. 21, 2009 |
| 7523230 |
Device and method for maximizing performance on a memory interface with a variable number of channels |
Apr. 21, 2009 |
| 7519796 |
Efficient utilization of a store buffer using counters |
Apr. 14, 2009 |
| 7519797 |
Hierarchical multi-precision pipeline counters |
Apr. 14, 2009 |
| 7516306 |
Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies |
Apr. 7, 2009 |
| 7516309 |
Method and apparatus for conditional memory ordering |
Apr. 7, 2009 |
| 7516310 |
Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor |
Apr. 7, 2009 |
| 7509484 |
Handling cache misses by selectively flushing the pipeline |
Mar. 24, 2009 |
| 7502917 |
High speed memory cloning facility via a lockless multiprocessor mechanism |
Mar. 10, 2009 |
| 7500049 |
Providing a backing store in user-level memory |
Mar. 3, 2009 |
| 7496673 |
SIMD-RISC microprocessor architecture |
Feb. 24, 2009 |
| 7496737 |
High priority guard transfer for execution control of dependent guarded instructions |
Feb. 24, 2009 |
| 7496721 |
Packet processor memory interface with late order binding |
Feb. 24, 2009 |
| 7493447 |
System and method for caching sequential programs |
Feb. 17, 2009 |
| 7493481 |
Direct hardware processing of internal data structure fields |
Feb. 17, 2009 |
| 7490178 |
Threshold on unblocking a processing node that is blocked due data packet passing |
Feb. 10, 2009 |
| 7487304 |
Packet processor memory interface with active packet list |
Feb. 3, 2009 |
| 7484017 |
Dequeuing from a host adapter two-dimensional queue |
Jan. 27, 2009 |
| 7484080 |
Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer |
Jan. 27, 2009 |
| 7480771 |
Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged |
Jan. 20, 2009 |
| 7480754 |
Assignment of queue execution modes using tag values |
Jan. 20, 2009 |
| 7480788 |
Command time-out managing apparatus |
Jan. 20, 2009 |
| 7478209 |
Packet processor memory interface with conflict detection and checkpoint repair |
Jan. 13, 2009 |
| 7475201 |
Packet processor memory interface with conditional delayed restart |
Jan. 6, 2009 |
| 7475200 |
Packet processor memory interface with write dependency list |
Jan. 6, 2009 |
| 7472390 |
Method and apparatus to enable execution of a thread in a multi-threaded computer system |
Dec. 30, 2008 |
| 7472260 |
Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion |
Dec. 30, 2008 |
| 7463640 |
Self-synchronous FIFO memory device |
Dec. 9, 2008 |
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