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Class Information
Number: 712/223
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing control > Logic operation instruction processing
Description: Subject matter for control of execution or processing of instruction data peculiar to logic operation (e.g., AND, OR, exclusive OR, etc.).










Sub-classes under this class:

Class Number Class Name Patents
712/224 Masking 179


Patents under this class:
1 2 3 4 5

Patent Number Title Of Patent Date Issued
6125442 Method, system and data structures for computer software application development and execution Sep. 26, 2000
6119216 Microprocessor capable of unpacking packed data in response to a unpack instruction Sep. 12, 2000
6112291 Method and apparatus for performing a shift instruction with saturate by examination of an operand prior to shifting Aug. 29, 2000
6098087 Method and apparatus for performing shift operations on packed data Aug. 1, 2000
6088744 Multiport data buffer having multi level caching wherein each data port has a FIFO buffer coupled thereto Jul. 11, 2000
6088792 Avoiding processor serialization after an S/390 SPKA instruction Jul. 11, 2000
6088791 Computer processor system for implementing the ESA/390 STOSM and STNSM instructions without serialization or artificially extending processor execution time Jul. 11, 2000
6049864 Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor Apr. 11, 2000
6044457 State machine controller capable of producing result per clock cycle using wait/no wait and empty signals to control the advancing of data in pipeline Mar. 28, 2000
6029244 Microprocessor including an efficient implementation of extreme value instructions Feb. 22, 2000
6014738 Method for computing a difference in a digital processing system Jan. 11, 2000
6006286 System for controlling data packet transfers by associating plurality of data packet transfer control instructions in packet control list including plurality of related logical functions Dec. 21, 1999
6006316 Performing SIMD shift and arithmetic operation in non-SIMD architecture by operation on packed data of sub-operands and carry over-correction Dec. 21, 1999
5995748 Three input arithmetic logic unit with shifter and/or mask generator Nov. 30, 1999
5987603 Apparatus and method for reversing bits using a shifter Nov. 16, 1999
5968164 Mixed-endian computing environment for a conventional bi-endian computer system Oct. 19, 1999
5961575 Microprocessor having combined shift and rotate circuit Oct. 5, 1999
5958038 Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation Sep. 28, 1999
5948098 Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines Sep. 7, 1999
5946483 Devices, systems and methods for conditional instructions Aug. 31, 1999
5930519 Distributed branch logic system and method for a geometry accelerator Jul. 27, 1999
5926645 Method and system for enabling multiple store instruction completions in a processing system Jul. 20, 1999
5918035 Method for processor modeling in code generation and instruction set simulation Jun. 29, 1999
5909572 System and method for conditionally moving an operand from a source register to a destination register Jun. 1, 1999
5896289 Output weighted partitioning method for a control program in a highly distributed control system Apr. 20, 1999
5889983 Compare and exchange operation in a processing system Mar. 30, 1999
5880746 Apparatus for forming a sum in a signal processing system Mar. 9, 1999
5881259 Input operand size and hi/low word selection control in data processing systems Mar. 9, 1999
5881275 Method for unpacking a plurality of packed data into a result packed data Mar. 9, 1999
5881274 Method and apparatus for performing add and rotate as a single instruction within a processor Mar. 9, 1999
5854929 Method of generating code for programmable processors, code generator and application thereof Dec. 29, 1998
5838985 Parallel processor with memory/ALU inhibiting feature Nov. 17, 1998
5838941 Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers Nov. 17, 1998
5828859 Method and apparatus for setting the status mode of a central processing unit Oct. 27, 1998
5818739 Processor for performing shift operations on packed data Oct. 6, 1998
5819101 Method for packing a plurality of packed data elements in response to a pack instruction Oct. 6, 1998
5812845 Method for generating an object code for a pipeline computer process to reduce swapping instruction set Sep. 22, 1998
5808889 System and method for identifying and correcting computer operations involving two digit year dates Sep. 15, 1998
5802336 Microprocessor capable of unpacking packed data Sep. 1, 1998
5799203 System for receiving peripheral device capability information and selectively disabling corresponding processing unit function when the device failing to support such function Aug. 25, 1998
5790882 Programmable logic device placement method utilizing weighting function to facilitate pin locking Aug. 4, 1998
5734880 Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections Mar. 31, 1998
5734874 Central processing unit with integrated graphics functions Mar. 31, 1998
5729482 Microprocessor shifter using rotation and masking operations Mar. 17, 1998
5706488 Data processing system and method thereof Jan. 6, 1998
5706469 Data processing system controlling bus access to an arbitrary sized memory area Jan. 6, 1998
5696954 Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically an Dec. 9, 1997
5682339 Method for performing rotate through carry using a 32 bit barrel shifter and counter Oct. 28, 1997
5666298 Method for performing shift operations on packed data Sep. 9, 1997
5657484 Method for carrying out a boolean operation between any two bits of any two registers Aug. 12, 1997

1 2 3 4 5










 
 
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