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Class Information
Number: 712/223
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing control > Logic operation instruction processing
Description: Subject matter for control of execution or processing of instruction data peculiar to logic operation (e.g., AND, OR, exclusive OR, etc.).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7219214 |
Data processing apparatus and method for moving data elements between a chosen lane of parallel processing in registers and a structure within memory |
May. 15, 2007 |
| 7174428 |
Method and system for transforming memory location references in instructions |
Feb. 6, 2007 |
| 7174014 |
Method and system for performing permutations with bit permutation instructions |
Feb. 6, 2007 |
| 7146491 |
Apparatus and method for generating constant values |
Dec. 5, 2006 |
| 7120781 |
General purpose register file architecture for aligned simd |
Oct. 10, 2006 |
| 7117232 |
Method and apparatus for providing packed shift operations in a processor |
Oct. 3, 2006 |
| 7114055 |
Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word |
Sep. 26, 2006 |
| 7047397 |
Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALU |
May. 16, 2006 |
| 7028107 |
Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) |
Apr. 11, 2006 |
| 7028170 |
Processing architecture having a compare capability |
Apr. 11, 2006 |
| 7003653 |
Method for rapid interpretation of results returned by a parallel compare instruction |
Feb. 21, 2006 |
| 6999454 |
Information routing system and apparatus |
Feb. 14, 2006 |
| 6986023 |
Conditional execution of coprocessor instruction based on main processor arithmetic flags |
Jan. 10, 2006 |
| 6978359 |
Microprocessor and method of aligning unaligned data loaded from memory using a set shift amount register instruction |
Dec. 20, 2005 |
| 6976155 |
Method and apparatus for communicating between processing entities in a multi-processor |
Dec. 13, 2005 |
| 6973551 |
Data storage system having atomic memory operation |
Dec. 6, 2005 |
| 6965960 |
xDSL symbol processor and method of operating same |
Nov. 15, 2005 |
| 6961846 |
Data processing unit, microprocessor, and method for performing an instruction |
Nov. 1, 2005 |
| 6934828 |
Decoupling floating point linear address |
Aug. 23, 2005 |
| 6931517 |
Pop-compare micro instruction for repeat string operations |
Aug. 16, 2005 |
| 6918029 |
Method and system for executing conditional instructions using a test register address that points to a test register from which a test code is selected |
Jul. 12, 2005 |
| 6918028 |
Pipelined processor including a loosely coupled side pipe |
Jul. 12, 2005 |
| 6901503 |
Data processing circuits and interfaces |
May. 31, 2005 |
| 6901420 |
Method and apparatus for performing packed shift operations |
May. 31, 2005 |
| 6898698 |
Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof |
May. 24, 2005 |
| 6892295 |
Processing architecture having an array bounds check capability |
May. 10, 2005 |
| 6842728 |
Time-multiplexing data between asynchronous clock domains within cycle simulation and emulation environments |
Jan. 11, 2005 |
| 6842852 |
System and method for controlling conditional branching utilizing a control instruction having a reduced word length |
Jan. 11, 2005 |
| 6834337 |
System and method for enabling multiple signed independent data elements per register |
Dec. 21, 2004 |
| 6829696 |
Data processing system with register store/load utilizing data packing/unpacking |
Dec. 7, 2004 |
| 6816961 |
Processing architecture having field swapping capability |
Nov. 9, 2004 |
| 6791705 |
Communication control apparatus and method |
Sep. 14, 2004 |
| 6763406 |
Noise reduction system and method for reducing switching noise in an interface to a large width bus |
Jul. 13, 2004 |
| 6757813 |
Processor |
Jun. 29, 2004 |
| 6757819 |
Microprocessor with instructions for shifting data responsive to a signed count value |
Jun. 29, 2004 |
| 6757820 |
Decompression bit processing with a general purpose alignment tool |
Jun. 29, 2004 |
| 6748518 |
Multi-level multiprocessor speculation mechanism |
Jun. 8, 2004 |
| 6748521 |
Microprocessor with instruction for saturating and packing data |
Jun. 8, 2004 |
| 6745319 |
Microprocessor with instructions for shuffling and dealing data |
Jun. 1, 2004 |
| 6738793 |
Processor capable of executing packed shift operations |
May. 18, 2004 |
| 6731294 |
Vector engine with pre-accumulation buffer and method therefore |
May. 4, 2004 |
| 6718459 |
Device and method for arithmetic processing |
Apr. 6, 2004 |
| 6718456 |
Parallel pack instruction method and apparatus |
Apr. 6, 2004 |
| 6704564 |
Method and system for controlling message transmission and acceptance by a telecommunications device |
Mar. 9, 2004 |
| 6687899 |
Relocation format for linking |
Feb. 3, 2004 |
| 6675376 |
System and method for fusing instructions |
Jan. 6, 2004 |
| 6671797 |
Microprocessor with expand instruction for forming a mask from one bit |
Dec. 30, 2003 |
| 6606670 |
Circuit serial programming of default configuration |
Aug. 12, 2003 |
| 6591357 |
Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements |
Jul. 8, 2003 |
| 6587939 |
Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions |
Jul. 1, 2003 |
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