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Class Information
Number: 712/221
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing control > Arithmetic operation instruction processing
Description: Subject matter for control of execution or processing of instruction data peculiar to arithmetic operation (e.g., add, subtract, multiply, etc.).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620764 |
System, apparatus and method for data path routing configurable to perform dynamic bit permutations |
Nov. 17, 2009 |
| 7590828 |
Processing a data word in a plurality of processing cycles |
Sep. 15, 2009 |
| 7587582 |
Method and apparatus for parallel arithmetic operations |
Sep. 8, 2009 |
| 7554464 |
Method and system for processing data having a pattern of repeating bits |
Jun. 30, 2009 |
| 7555635 |
Data processing device |
Jun. 30, 2009 |
| 7546443 |
Providing extended precision in SIMD vector arithmetic operations |
Jun. 9, 2009 |
| 7533249 |
Reconfigurable integrated circuit, circuit reconfiguration method and circuit reconfiguration apparatus |
May. 12, 2009 |
| 7525457 |
Transforming design objects in a computer by converting data sets between data set types |
Apr. 28, 2009 |
| 7523261 |
Method and circuit arrangement for adapting a program to suit a buffer store |
Apr. 21, 2009 |
| 7502029 |
Instruction folding mechanism, method for performing the same and pixel processing system employing the same |
Mar. 10, 2009 |
| 7496736 |
Method of efficient digital processing of multi-dimensional data |
Feb. 24, 2009 |
| 7475229 |
Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit |
Jan. 6, 2009 |
| 7464251 |
Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements |
Dec. 9, 2008 |
| 7457940 |
System and method for managing data |
Nov. 25, 2008 |
| 7454594 |
Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements |
Nov. 18, 2008 |
| 7447871 |
Data access program instruction encoding |
Nov. 4, 2008 |
| 7441106 |
Distributed processing in a multiple processing unit environment |
Oct. 21, 2008 |
| 7434034 |
SIMD processor executing min/max instructions |
Oct. 7, 2008 |
| 7430656 |
System and method of converting data formats and communicating between execution units |
Sep. 30, 2008 |
| 7424594 |
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture |
Sep. 9, 2008 |
| 7409528 |
Digital signal processing architecture with a wide memory bandwidth and a memory mapping method thereof |
Aug. 5, 2008 |
| 7395302 |
Method and apparatus for performing horizontal addition and subtraction |
Jul. 1, 2008 |
| 7392275 |
Method and apparatus for performing efficient transformations with horizontal addition and subtraction |
Jun. 24, 2008 |
| 7392368 |
Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements |
Jun. 24, 2008 |
| 7389406 |
Apparatus and methods for utilization of splittable execution units of a processor |
Jun. 17, 2008 |
| 7366882 |
Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions |
Apr. 29, 2008 |
| 7363471 |
Apparatus, system, and method of dynamic binary translation supporting a denormal input handling mechanism |
Apr. 22, 2008 |
| 7353516 |
Data flow control for adaptive integrated circuitry |
Apr. 1, 2008 |
| 7346761 |
Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle |
Mar. 18, 2008 |
| 7343472 |
Processor having a finite field arithmetic unit utilizing an array of multipliers and adders |
Mar. 11, 2008 |
| 7308560 |
Processing unit |
Dec. 11, 2007 |
| 7290121 |
Method and data processor with reduced stalling due to operand dependencies |
Oct. 30, 2007 |
| 7284117 |
Processor that predicts floating point instruction latency based on predicted precision |
Oct. 16, 2007 |
| 7269718 |
Method and apparatus for verifying data types to be used for instructions and casting data types if needed |
Sep. 11, 2007 |
| 7249243 |
Control word prediction and varying recovery upon comparing actual to set of stored words |
Jul. 24, 2007 |
| 7240184 |
Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations |
Jul. 3, 2007 |
| 7237055 |
System, apparatus and method for data path routing configurable to perform dynamic bit permutations |
Jun. 26, 2007 |
| 7237089 |
SIMD operation method and SIMD operation apparatus that implement SIMD operations without a large increase in the number of instructions |
Jun. 26, 2007 |
| 7231510 |
Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof |
Jun. 12, 2007 |
| 7216217 |
Programmable processor with group floating-point operations |
May. 8, 2007 |
| 7216138 |
Method and apparatus for floating point operations and format conversion operations |
May. 8, 2007 |
| 7212959 |
Method and apparatus for accumulating floating point values |
May. 1, 2007 |
| 7206927 |
Pipelined processor method and circuit with interleaving of iterative operations |
Apr. 17, 2007 |
| 7191316 |
Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream |
Mar. 13, 2007 |
| 7159100 |
Method for providing extended precision in SIMD vector arithmetic operations |
Jan. 2, 2007 |
| 7149877 |
Byte execution unit for carrying out byte instructions in a processor |
Dec. 12, 2006 |
| 7149882 |
Processor with instructions that operate on different data types stored in the same single logical register file |
Dec. 12, 2006 |
| 7146491 |
Apparatus and method for generating constant values |
Dec. 5, 2006 |
| 7139901 |
Extended instruction set for packet processing applications |
Nov. 21, 2006 |
| 7139900 |
Data packet arithmetic logic devices and methods |
Nov. 21, 2006 |
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