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Class Information
Number: 712/22
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Array processor > Array processor operation > Single instruction, multiple data (simd)
Description: Subject matter wherein the array processor operates in a single instruction, multiple data mode.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7599489 |
Accelerating cryptographic hash computations |
Oct. 6, 2009 |
| 7596679 |
Interconnections in SIMD processor architectures |
Sep. 29, 2009 |
| 7594095 |
Multithreaded SIMD parallel processor with launching of groups of threads |
Sep. 22, 2009 |
| 7584342 |
Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue |
Sep. 1, 2009 |
| 7580412 |
System and method for generating header error control byte for Asynchronous Transfer Mode cell |
Aug. 25, 2009 |
| 7568085 |
Scalable FPGA fabric architecture with protocol converting bus interface and reconfigurable communication path to SIMD processing elements |
Jul. 28, 2009 |
| 7565287 |
Methods and apparatus for efficient vocoder implementations |
Jul. 21, 2009 |
| 7565514 |
Parallel condition code generation for SIMD operations |
Jul. 21, 2009 |
| 7546443 |
Providing extended precision in SIMD vector arithmetic operations |
Jun. 9, 2009 |
| 7539846 |
SIMD processor with a subroutine control unit |
May. 26, 2009 |
| 7536532 |
Merge operations of data arrays based on SIMD instructions |
May. 19, 2009 |
| 7526630 |
Parallel data processing apparatus |
Apr. 28, 2009 |
| 7516299 |
Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions |
Apr. 7, 2009 |
| 7509602 |
Compact processor element for a scalable digital logic verification and emulation system |
Mar. 24, 2009 |
| 7506135 |
Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements |
Mar. 17, 2009 |
| 7506136 |
Parallel data processing apparatus |
Mar. 17, 2009 |
| 7496673 |
SIMD-RISC microprocessor architecture |
Feb. 24, 2009 |
| 7490190 |
Method and system for local memory addressing in single instruction, multiple data computer system |
Feb. 10, 2009 |
| 7483595 |
Image processing method and device |
Jan. 27, 2009 |
| 7484076 |
Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P) |
Jan. 27, 2009 |
| 7480785 |
Parallel processing device and parallel processing method |
Jan. 20, 2009 |
| 7467288 |
Vector register file with arbitrary vector addressing |
Dec. 16, 2008 |
| 7467286 |
Executing partial-width packed data instructions |
Dec. 16, 2008 |
| 7460989 |
Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language |
Dec. 2, 2008 |
| 7457941 |
Vector processing system |
Nov. 25, 2008 |
| 7453882 |
Apparatus and method for asynchronously controlling data transfers across long wires |
Nov. 18, 2008 |
| 7454749 |
Scalable parallel processing on shared memory computers |
Nov. 18, 2008 |
| 7454594 |
Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements |
Nov. 18, 2008 |
| 7451294 |
Apparatus and method for two micro-operation flow using source override |
Nov. 11, 2008 |
| 7447873 |
Multithreaded SIMD parallel processor with loading of groups of threads |
Nov. 4, 2008 |
| 7444496 |
Apparatus, system, and method for determining the consistency of a database |
Oct. 28, 2008 |
| 7441098 |
Conditional execution of instructions in a computer |
Oct. 21, 2008 |
| 7441099 |
Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit |
Oct. 21, 2008 |
| 7412587 |
Parallel operation processor utilizing SIMD data transfers |
Aug. 12, 2008 |
| 7401204 |
Parallel Processor efficiently executing variable instruction word |
Jul. 15, 2008 |
| 7395531 |
Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements |
Jul. 1, 2008 |
| 7392368 |
Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements |
Jun. 24, 2008 |
| 7392329 |
System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices |
Jun. 24, 2008 |
| 7383421 |
Cellular engine for a data processing system |
Jun. 3, 2008 |
| 7376812 |
Vector co-processor for configurable and extensible processor architecture |
May. 20, 2008 |
| 7373488 |
Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values |
May. 13, 2008 |
| 7367026 |
Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization |
Apr. 29, 2008 |
| 7363472 |
Memory access consolidation for SIMD processing elements having access indicators |
Apr. 22, 2008 |
| 7363478 |
Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index |
Apr. 22, 2008 |
| 7360063 |
Method for SIMD-oriented management of register maps for map-based indirect register-file access |
Apr. 15, 2008 |
| 7350057 |
Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction |
Mar. 25, 2008 |
| 7328371 |
Core redundancy in a chip multiprocessor for highly reliable systems |
Feb. 5, 2008 |
| 7315932 |
Data processing system having instruction specifiers for SIMD register operands and method thereof |
Jan. 1, 2008 |
| 7313788 |
Vectorization in a SIMdD DSP architecture |
Dec. 25, 2007 |
| 7313646 |
Interfacing of functional modules in an on-chip system |
Dec. 25, 2007 |
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