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Class Information
Number: 712/219
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Dynamic instruction dependency checking, monitoring or conflict resolution > Reducing an impact of a stall or pipeline bubble
Description: Subject matter including means or steps for allowing an instruction execution to catch up with other instruction in a pipeline without flushing that execution pipeline.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620799 |
Using a modified value GPR to enhance lookahead prefetch |
Nov. 17, 2009 |
| 7594097 |
Microprocessor output ports and control of instructions provided therefrom |
Sep. 22, 2009 |
| 7594078 |
D-cache miss prediction and scheduling |
Sep. 22, 2009 |
| 7552318 |
Branch lookahead prefetch for microprocessors |
Jun. 23, 2009 |
| 7529913 |
Late allocation of registers |
May. 5, 2009 |
| 7530072 |
Method to segregate suspicious threads in a hosted environment to prevent CPU resource exhaustion from hung threads |
May. 5, 2009 |
| 7516306 |
Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies |
Apr. 7, 2009 |
| 7496921 |
Processing block with integrated light weight multi-threading support |
Feb. 24, 2009 |
| 7487337 |
Back-end renaming in a continual flow processor pipeline |
Feb. 3, 2009 |
| 7475227 |
Method of stalling one or more stages in an interlocked synchronous pipeline |
Jan. 6, 2009 |
| 7472259 |
Multi-cycle instructions |
Dec. 30, 2008 |
| 7469407 |
Method for resource balancing using dispatch flush in a simultaneous multithread processor |
Dec. 23, 2008 |
| 7464242 |
Method of load/store dependencies detection with dynamically changing address length |
Dec. 9, 2008 |
| 7454600 |
Method and apparatus for assigning thread priority in a processor or the like |
Nov. 18, 2008 |
| 7454598 |
Controlling out of order execution pipelines issue tagging |
Nov. 18, 2008 |
| 7447879 |
Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss |
Nov. 4, 2008 |
| 7444498 |
Load lookahead prefetch for microprocessors |
Oct. 28, 2008 |
| 7441101 |
Thread-aware instruction fetching in a multithreaded embedded processor |
Oct. 21, 2008 |
| 7441245 |
Phasing for a multi-threaded network processor |
Oct. 21, 2008 |
| 7437539 |
Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline |
Oct. 14, 2008 |
| 7434033 |
Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline |
Oct. 7, 2008 |
| 7421567 |
Using a modified value GPR to enhance lookahead prefetch |
Sep. 2, 2008 |
| 7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers |
Sep. 2, 2008 |
| 7418625 |
Deadlock detection and recovery logic for flow control based data path design |
Aug. 26, 2008 |
| 7406588 |
Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer |
Jul. 29, 2008 |
| 7404067 |
Method and apparatus for efficient utilization for prescient instruction prefetch |
Jul. 22, 2008 |
| 7401211 |
Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor |
Jul. 15, 2008 |
| 7398358 |
Method and apparatus for high performance branching in pipelined microsystems |
Jul. 8, 2008 |
| 7366877 |
Speculative instruction issue in a simultaneously multithreaded processor |
Apr. 29, 2008 |
| 7363468 |
Load address dependency mechanism system and method in a high frequency, low power processor system |
Apr. 22, 2008 |
| 7363474 |
Method and apparatus for suspending execution of a thread until a specified memory access occurs |
Apr. 22, 2008 |
| 7360064 |
Thread interleaving in a multithreaded embedded processor |
Apr. 15, 2008 |
| 7356675 |
Data processor |
Apr. 8, 2008 |
| 7346760 |
Data processing apparatus of high speed process using memory of low speed and low power consumption |
Mar. 18, 2008 |
| 7343476 |
Intelligent SMT thread hang detect taking into account shared resource contention/blocking |
Mar. 11, 2008 |
| 7337305 |
Method and pipeline architecture for processing multiple swap requests to reduce latency |
Feb. 26, 2008 |
| 7328330 |
Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor |
Feb. 5, 2008 |
| 7318145 |
Random slip generator |
Jan. 8, 2008 |
| 7316021 |
Switching method in a multi-threaded processor |
Jan. 1, 2008 |
| 7313673 |
Fine grained multi-thread dispatch block mechanism |
Dec. 25, 2007 |
| 7310741 |
Phase adjusted delay loop executed by determining a number of NOPs based on a modulus value |
Dec. 18, 2007 |
| 7308593 |
Interlocked synchronous pipeline clock gating |
Dec. 11, 2007 |
| 7293163 |
Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency |
Nov. 6, 2007 |
| 7290121 |
Method and data processor with reduced stalling due to operand dependencies |
Oct. 30, 2007 |
| 7281120 |
Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor |
Oct. 9, 2007 |
| 7274369 |
Digital image compositing using a programmable graphics processor |
Sep. 25, 2007 |
| 7266674 |
Programmable delayed dispatch in a multi-threaded pipeline |
Sep. 4, 2007 |
| 7266675 |
Processor including a register file and method for computing flush masks in a multi-threaded processing system |
Sep. 4, 2007 |
| 7260707 |
Variable length instruction pipeline |
Aug. 21, 2007 |
| 7257699 |
Selective execution of deferred instructions in a processor that supports speculative execution |
Aug. 14, 2007 |
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