| |
 |
|
Class Information
Number: 712/218
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Dynamic instruction dependency checking, monitoring or conflict resolution > Commitment control or register bypass
Description: Subject matter including means or steps for controlling the writing of results to registers and for bypassing results around registers to eliminate or alleviate data availability conflicts.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5946468 |
Reorder buffer having an improved future file for storing speculative instruction execution results |
Aug. 31, 1999 |
| 5941984 |
Data processing device |
Aug. 24, 1999 |
| 5937430 |
Buffer circuit with control device to directly output input data or to output input data written in storage device |
Aug. 10, 1999 |
| 5937178 |
Register file for registers with multiple addressable sizes using read-modify-write for register file update |
Aug. 10, 1999 |
| 5933618 |
Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction |
Aug. 3, 1999 |
| 5931942 |
Pipeline data processing apparatus of reduced circuit scale |
Aug. 3, 1999 |
| 5930521 |
Reorder buffer architecture for accessing partial word operands |
Jul. 27, 1999 |
| 5919256 |
Operand cache addressed by the instruction address for reducing latency of read instruction |
Jul. 6, 1999 |
| 5918034 |
Method for decoupling pipeline stages |
Jun. 29, 1999 |
| 5903741 |
Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions |
May. 11, 1999 |
| 5901302 |
Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions |
May. 4, 1999 |
| 5898854 |
Apparatus for indicating an oldest non-retired load operation in an array |
Apr. 27, 1999 |
| 5889974 |
Method and apparatus for the detection of reordering hazards |
Mar. 30, 1999 |
| 5887185 |
Interface for coupling a floating point unit to a reorder buffer |
Mar. 23, 1999 |
| 5887152 |
Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions |
Mar. 23, 1999 |
| 5884062 |
Microprocessor with pipeline status integrity logic for handling multiple stage writeback exceptions |
Mar. 16, 1999 |
| 5881306 |
Instruction fetch bandwidth analysis |
Mar. 9, 1999 |
| 5881265 |
Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts |
Mar. 9, 1999 |
| 5878244 |
Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions receiv |
Mar. 2, 1999 |
| 5878252 |
Microprocessor configured to generate help instructions for performing data cache fills |
Mar. 2, 1999 |
| 5872949 |
Apparatus and method for managing data flow dependencies arising from out-of-order execution, by an execution unit, of an instruction series input from an instruction source |
Feb. 16, 1999 |
| 5872950 |
Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages |
Feb. 16, 1999 |
| 5872951 |
Reorder buffer having a future file for storing speculative instruction execution results |
Feb. 16, 1999 |
| 5870581 |
Method and apparatus for performing concurrent write operations to a single-write-input register file and an accumulator register |
Feb. 9, 1999 |
| 5870582 |
Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched |
Feb. 9, 1999 |
| 5870580 |
Decoupled forwarding reorder buffer configured to allocate storage in chunks for instructions having unresolved dependencies |
Feb. 9, 1999 |
| 5867683 |
Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations |
Feb. 2, 1999 |
| 5867684 |
Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction |
Feb. 2, 1999 |
| 5862399 |
Write control unit |
Jan. 19, 1999 |
| 5860017 |
Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction |
Jan. 12, 1999 |
| 5842036 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution |
Nov. 24, 1998 |
| 5838942 |
Panic trap system and method |
Nov. 17, 1998 |
| 5838943 |
Apparatus for speculatively storing and restoring data to a cache memory |
Nov. 17, 1998 |
| 5838944 |
System for storing processor register data after a mispredicted branch |
Nov. 17, 1998 |
| 5835747 |
Hierarchical scan logic for out-of-order load/store execution control |
Nov. 10, 1998 |
| 5832293 |
Processor architecture providing speculative, out of order execution of instructions and trap handling |
Nov. 3, 1998 |
| 5832292 |
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution |
Nov. 3, 1998 |
| 5826055 |
System and method for retiring instructions in a superscalar microprocessor |
Oct. 20, 1998 |
| 5826094 |
Register alias table update to indicate architecturally visible state |
Oct. 20, 1998 |
| 5822575 |
Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction |
Oct. 13, 1998 |
| 5812845 |
Method for generating an object code for a pipeline computer process to reduce swapping instruction set |
Sep. 22, 1998 |
| 5812813 |
Apparatus and method for of register changes during execution of a micro instruction tracking sequence |
Sep. 22, 1998 |
| 5809324 |
Multiple instruction dispatch system for pipelined microprocessor without branch breaks |
Sep. 15, 1998 |
| 5809325 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution |
Sep. 15, 1998 |
| 5805852 |
Parallel processor performing bypass control by grasping portions in which instructions exist |
Sep. 8, 1998 |
| 5805853 |
Superscalar microprocessor including flag operand renaming and forwarding apparatus |
Sep. 8, 1998 |
| 5802346 |
Method and system for minimizing the delay in executing branch-on-register instructions |
Sep. 1, 1998 |
| 5802340 |
Method and system of executing speculative store instructions in a parallel processing computer system |
Sep. 1, 1998 |
| 5802339 |
Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit |
Sep. 1, 1998 |
| 5802337 |
Method and apparatus for executing load instructions speculatively |
Sep. 1, 1998 |
|
|
|
