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Class Information
Number: 712/218
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Dynamic instruction dependency checking, monitoring or conflict resolution > Commitment control or register bypass
Description: Subject matter including means or steps for controlling the writing of results to registers and for bypassing results around registers to eliminate or alleviate data availability conflicts.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7613906 |
Advanced load value check enhancement |
Nov. 3, 2009 |
| 7613905 |
Partial register forwarding for CPUs with unequal delay functional units |
Nov. 3, 2009 |
| 7613908 |
Selective hardware lock disabling |
Nov. 3, 2009 |
| 7590827 |
Processor and instruction control method having a storage of latest register for updating data of source operands, and instruction control |
Sep. 15, 2009 |
| 7587585 |
Flag management in processors enabled for speculative execution of micro-operation traces |
Sep. 8, 2009 |
| 7581083 |
Operation processing device, system and method having register-to-register addressing |
Aug. 25, 2009 |
| 7568088 |
Flag management in processors enabled for speculative execution of micro-operation traces |
Jul. 28, 2009 |
| 7568089 |
Flag management in processors enabled for speculative execution of micro-operation traces |
Jul. 28, 2009 |
| 7555632 |
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution |
Jun. 30, 2009 |
| 7543134 |
Apparatus and method for extending a microprocessor instruction set |
Jun. 2, 2009 |
| 7536432 |
Parallel merge/sort processing device, method, and program for sorting data strings |
May. 19, 2009 |
| 7529913 |
Late allocation of registers |
May. 5, 2009 |
| 7523295 |
Processor and method of grouping and executing dependent instructions in a packet |
Apr. 21, 2009 |
| 7523296 |
System and method for handling exceptions and branch mispredictions in a superscalar microprocessor |
Apr. 21, 2009 |
| 7519794 |
High performance architecture for a writeback stage |
Apr. 14, 2009 |
| 7516302 |
Efficient use of co-processor in platform independent instruction machine by controlling result transfer and translation and transfer timing of subsequent instruction based on instruction type |
Apr. 7, 2009 |
| 7516305 |
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor |
Apr. 7, 2009 |
| 7506140 |
Return data selector employing barrel-incrementer-based round-robin apparatus |
Mar. 17, 2009 |
| 7500086 |
Start transactional execution (STE) instruction to support transactional program execution |
Mar. 3, 2009 |
| 7496735 |
Method and apparatus for incremental commitment to architectural state in a microprocessor |
Feb. 24, 2009 |
| 7496916 |
Service and recovery using multi-flow redundant request processing |
Feb. 24, 2009 |
| 7496721 |
Packet processor memory interface with late order binding |
Feb. 24, 2009 |
| 7493508 |
Information processing device, method, and program |
Feb. 17, 2009 |
| 7487335 |
Method and apparatus for accessing registers during deferred execution |
Feb. 3, 2009 |
| 7487304 |
Packet processor memory interface with active packet list |
Feb. 3, 2009 |
| 7484078 |
Pipelined asynchronous instruction processor having two write pipeline stages with control of write ordering from stages to maintain sequential program ordering |
Jan. 27, 2009 |
| 7478379 |
Method for minimizing spill in code scheduled by a list scheduler |
Jan. 13, 2009 |
| 7478276 |
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor |
Jan. 13, 2009 |
| 7478226 |
Processing bypass directory tracking system and method |
Jan. 13, 2009 |
| 7478209 |
Packet processor memory interface with conflict detection and checkpoint repair |
Jan. 13, 2009 |
| 7475201 |
Packet processor memory interface with conditional delayed restart |
Jan. 6, 2009 |
| 7475225 |
Method and apparatus for microarchitecture partitioning of execution clusters |
Jan. 6, 2009 |
| 7475200 |
Packet processor memory interface with write dependency list |
Jan. 6, 2009 |
| 7475226 |
System for managing data dependency using bit field instruction destination vector identifying destination for execution results |
Jan. 6, 2009 |
| 7472260 |
Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion |
Dec. 30, 2008 |
| 7472258 |
Dynamically shared group completion table between multiple threads |
Dec. 30, 2008 |
| 7464242 |
Method of load/store dependencies detection with dynamically changing address length |
Dec. 9, 2008 |
| 7454532 |
Stream data interface for processing system |
Nov. 18, 2008 |
| 7454598 |
Controlling out of order execution pipelines issue tagging |
Nov. 18, 2008 |
| 7444497 |
Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support |
Oct. 28, 2008 |
| 7426630 |
Arbitration of window swap operations |
Sep. 16, 2008 |
| 7424598 |
Data processor |
Sep. 9, 2008 |
| 7421567 |
Using a modified value GPR to enhance lookahead prefetch |
Sep. 2, 2008 |
| 7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers |
Sep. 2, 2008 |
| 7418577 |
Fail instruction to support transactional program execution |
Aug. 26, 2008 |
| 7418578 |
Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction |
Aug. 26, 2008 |
| 7415601 |
Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters |
Aug. 19, 2008 |
| 7415597 |
Processor with dependence mechanism to predict whether a load is dependent on older store |
Aug. 19, 2008 |
| 7395415 |
Method and apparatus to provide a source operand for an instruction in a processor |
Jul. 1, 2008 |
| 7395416 |
Computer processing system employing an instruction reorder buffer |
Jul. 1, 2008 |
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