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Class Information
Number: 712/218
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Dynamic instruction dependency checking, monitoring or conflict resolution > Commitment control or register bypass
Description: Subject matter including means or steps for controlling the writing of results to registers and for bypassing results around registers to eliminate or alleviate data availability conflicts.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7426630 |
Arbitration of window swap operations |
Sep. 16, 2008 |
| 7424598 |
Data processor |
Sep. 9, 2008 |
| 7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers |
Sep. 2, 2008 |
| 7421567 |
Using a modified value GPR to enhance lookahead prefetch |
Sep. 2, 2008 |
| 7418577 |
Fail instruction to support transactional program execution |
Aug. 26, 2008 |
| 7418578 |
Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction |
Aug. 26, 2008 |
| 7415597 |
Processor with dependence mechanism to predict whether a load is dependent on older store |
Aug. 19, 2008 |
| 7415601 |
Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters |
Aug. 19, 2008 |
| 7395416 |
Computer processing system employing an instruction reorder buffer |
Jul. 1, 2008 |
| 7395415 |
Method and apparatus to provide a source operand for an instruction in a processor |
Jul. 1, 2008 |
| 7386707 |
Processor and program execution method capable of efficient program execution |
Jun. 10, 2008 |
| 7380103 |
Apparatus and method for selective control of results write back |
May. 27, 2008 |
| 7380104 |
Method and apparatus for back to back issue of dependent instructions in an out of order issue queue |
May. 27, 2008 |
| 7376816 |
Method and systems for executing load instructions that achieve sequential load consistency |
May. 20, 2008 |
| 7373486 |
Partially decoded register renamer |
May. 13, 2008 |
| 7373485 |
Clustered superscalar processor with communication control between clusters |
May. 13, 2008 |
| 7373484 |
Controlling writes to non-renamed register space in an out-of-order execution microprocessor |
May. 13, 2008 |
| 7373483 |
Mechanism for extending the number of registers in a microprocessor |
May. 13, 2008 |
| 7370176 |
System and method for high frequency stall design |
May. 6, 2008 |
| 7370178 |
Method for latest producer tracking in an out-of-order processor, and applications thereof |
May. 6, 2008 |
| 7366879 |
Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses |
Apr. 29, 2008 |
| 7366880 |
Facilitating value prediction to support speculative program execution |
Apr. 29, 2008 |
| 7363470 |
System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor |
Apr. 22, 2008 |
| 7363625 |
Method for changing a thread priority in a simultaneous multithread processor |
Apr. 22, 2008 |
| 7353365 |
Implementing check instructions in each thread within a redundant multithreading environments |
Apr. 1, 2008 |
| 7350055 |
Tightly coupled accelerator |
Mar. 25, 2008 |
| 7343477 |
Efficient read after write bypass |
Mar. 11, 2008 |
| 7337305 |
Method and pipeline architecture for processing multiple swap requests to reduce latency |
Feb. 26, 2008 |
| 7330963 |
Resolving all previous potentially excepting architectural operations before issuing store architectural operation |
Feb. 12, 2008 |
| 7310723 |
Methods and systems employing a flag for deferring exception handling to a commit or rollback point |
Dec. 18, 2007 |
| 7302380 |
Simulation apparatus, method and program |
Nov. 27, 2007 |
| 7293163 |
Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency |
Nov. 6, 2007 |
| 7278010 |
Instruction execution apparatus comprising a commit stack entry unit |
Oct. 2, 2007 |
| 7278011 |
Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table |
Oct. 2, 2007 |
| 7275146 |
Instruction control device and method therefor |
Sep. 25, 2007 |
| 7269717 |
Method for reducing lock manipulation overhead during access to critical code sections |
Sep. 11, 2007 |
| 7266673 |
Speculation pointers to identify data-speculative operations in microprocessor |
Sep. 4, 2007 |
| 7263600 |
System and method for validating a memory file that links speculative results of load operations to register values |
Aug. 28, 2007 |
| 7263603 |
Method and apparatus for avoiding read-after-write hazards in an execute-ahead processor |
Aug. 28, 2007 |
| 7260706 |
Branch misprediction recovery using a side memory |
Aug. 21, 2007 |
| 7246219 |
Methods and apparatus to control functional blocks within a processor |
Jul. 17, 2007 |
| 7243215 |
System and method for utilizing a scoreboard to indicate information pertaining to pending register writes |
Jul. 10, 2007 |
| 7243216 |
Apparatus and method for updating a status register in an out of order execution pipeline based on most recently issued instruction information |
Jul. 10, 2007 |
| 7237096 |
Storing results of producer instructions to facilitate consumer instruction dependency tracking |
Jun. 26, 2007 |
| 7231510 |
Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof |
Jun. 12, 2007 |
| 7219349 |
Multi-threading techniques for a processor utilizing a replay queue |
May. 15, 2007 |
| 7216219 |
Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor |
May. 8, 2007 |
| 7213133 |
Method and apparatus for avoiding write-after-write hazards in an execute-ahead processor |
May. 1, 2007 |
| 7213130 |
Instruction rollback processor system, an instruction rollback method and an instruction rollback program |
May. 1, 2007 |
| 7200737 |
Processor with a replay system that includes a replay queue for improved throughput |
Apr. 3, 2007 |
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