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Class Information
Number: 712/216
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Dynamic instruction dependency checking, monitoring or conflict resolution
Description: Subject matter including means or steps for on-the-fly testing of instructions and operands to assess conflicts related to data or functional unit availability (e.g., identifying dependencies, attempting to resolve dependencies, or both).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620798 |
Latency tolerant pipeline synchronization |
Nov. 17, 2009 |
| 7617387 |
Methods and system for resolving simultaneous predicted branch instructions |
Nov. 10, 2009 |
| 7603527 |
Resolving false dependencies of speculative load instructions |
Oct. 13, 2009 |
| 7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation |
Oct. 13, 2009 |
| 7600097 |
Detecting raw hazards in an object-addressed memory hierarchy by comparing an object identifier and offset for a load instruction to object identifiers and offsets in a store queue |
Oct. 6, 2009 |
| 7600098 |
Method and system for efficient implementation of very large store buffer |
Oct. 6, 2009 |
| 7594097 |
Microprocessor output ports and control of instructions provided therefrom |
Sep. 22, 2009 |
| 7594227 |
Dependency graph parameter scoping |
Sep. 22, 2009 |
| 7590826 |
Speculative data value usage |
Sep. 15, 2009 |
| 7590825 |
Counter-based memory disambiguation techniques for selectively predicting load/store conflicts |
Sep. 15, 2009 |
| 7580914 |
Method and apparatus to improve execution of a stored program |
Aug. 25, 2009 |
| 7568197 |
Method and apparatus for interposing kernel symbols |
Jul. 28, 2009 |
| 7562206 |
Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions |
Jul. 14, 2009 |
| 7555634 |
Multiple data hazards detection and resolution unit |
Jun. 30, 2009 |
| 7555632 |
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution |
Jun. 30, 2009 |
| 7552247 |
Increased computer peripheral throughput by using data available withholding |
Jun. 23, 2009 |
| 7530072 |
Method to segregate suspicious threads in a hosted environment to prevent CPU resource exhaustion from hung threads |
May. 5, 2009 |
| 7526634 |
Counter-based delay of dependent thread group execution |
Apr. 28, 2009 |
| 7523295 |
Processor and method of grouping and executing dependent instructions in a packet |
Apr. 21, 2009 |
| 7523266 |
Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level |
Apr. 21, 2009 |
| 7502888 |
Symmetric multiprocessor system |
Mar. 10, 2009 |
| 7496921 |
Processing block with integrated light weight multi-threading support |
Feb. 24, 2009 |
| 7496899 |
Preventing loss of traced information in a data processing apparatus |
Feb. 24, 2009 |
| 7496735 |
Method and apparatus for incremental commitment to architectural state in a microprocessor |
Feb. 24, 2009 |
| 7496733 |
System and method of execution of register pointer instructions ahead of instruction issues |
Feb. 24, 2009 |
| 7493471 |
Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready |
Feb. 17, 2009 |
| 7493447 |
System and method for caching sequential programs |
Feb. 17, 2009 |
| 7490225 |
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number |
Feb. 10, 2009 |
| 7487380 |
Execution recovery escalation policy |
Feb. 3, 2009 |
| 7487336 |
Method for register allocation during instruction scheduling |
Feb. 3, 2009 |
| 7480771 |
Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged |
Jan. 20, 2009 |
| 7478226 |
Processing bypass directory tracking system and method |
Jan. 13, 2009 |
| 7475399 |
Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization |
Jan. 6, 2009 |
| 7469407 |
Method for resource balancing using dispatch flush in a simultaneous multithread processor |
Dec. 23, 2008 |
| 7464242 |
Method of load/store dependencies detection with dynamically changing address length |
Dec. 9, 2008 |
| 7464253 |
Tracking multiple dependent instructions with instruction queue pointer mapping table linked to a multiple wakeup table by a pointer |
Dec. 9, 2008 |
| 7461238 |
Simple load and store disambiguation and scheduling at predecode |
Dec. 2, 2008 |
| 7454599 |
Selecting multiple threads for substantially concurrent processing |
Nov. 18, 2008 |
| 7454598 |
Controlling out of order execution pipelines issue tagging |
Nov. 18, 2008 |
| 7451294 |
Apparatus and method for two micro-operation flow using source override |
Nov. 11, 2008 |
| 7451295 |
Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues |
Nov. 11, 2008 |
| 7448037 |
Method and data processing system having dynamic profile-directed feedback at runtime |
Nov. 4, 2008 |
| 7441107 |
Utilizing an advanced load address table for memory disambiguation in an out of order processor |
Oct. 21, 2008 |
| 7434002 |
Utilizing cache information to manage memory access and cache utilization |
Oct. 7, 2008 |
| 7430651 |
System and method for assigning tags to control instruction processing in a superscalar processor |
Sep. 30, 2008 |
| 7430653 |
Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking |
Sep. 30, 2008 |
| 7428631 |
Apparatus and method using different size rename registers for partial-bit and bulk-bit writes |
Sep. 23, 2008 |
| 7421567 |
Using a modified value GPR to enhance lookahead prefetch |
Sep. 2, 2008 |
| 7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers |
Sep. 2, 2008 |
| 7418552 |
Memory disambiguation for large instruction windows |
Aug. 26, 2008 |
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