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Class Information
Number: 712/215
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction issuing > Simultaneous issuance of multiple instructions
Description: Subject matter including means or steps for issuing plural instructions in parallel (e.g., superscalar, very long instruction word (VLIW)).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7617494 |
Process for running programs with selectable instruction length processors and corresponding processor system |
Nov. 10, 2009 |
| 7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation |
Oct. 13, 2009 |
| 7600221 |
Methods and apparatus of an architecture supporting execution of instructions in parallel |
Oct. 6, 2009 |
| 7594078 |
D-cache miss prediction and scheduling |
Sep. 22, 2009 |
| 7571301 |
Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors |
Aug. 4, 2009 |
| 7509482 |
Orderly processing ready entries from non-sequentially stored entries using arrival order matrix reordered upon removal of processed entries |
Mar. 24, 2009 |
| 7509483 |
Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors |
Mar. 24, 2009 |
| 7475223 |
Fetch-side instruction dispatch group formation |
Jan. 6, 2009 |
| 7472257 |
Rerouting VLIW instructions to accommodate execution units deactivated upon detection by dispatch units of dedicated instruction alerting multiple successive removed NOPs |
Dec. 30, 2008 |
| 7457938 |
Staggered execution stack for vector processing |
Nov. 25, 2008 |
| 7454597 |
Computer processing system employing an instruction schedule cache |
Nov. 18, 2008 |
| 7447879 |
Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss |
Nov. 4, 2008 |
| 7447887 |
Multithread processor |
Nov. 4, 2008 |
| 7441098 |
Conditional execution of instructions in a computer |
Oct. 21, 2008 |
| 7437544 |
Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction |
Oct. 14, 2008 |
| 7430653 |
Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking |
Sep. 30, 2008 |
| 7430651 |
System and method for assigning tags to control instruction processing in a superscalar processor |
Sep. 30, 2008 |
| 7430643 |
Multiple contexts for efficient use of translation lookaside buffer |
Sep. 30, 2008 |
| 7421571 |
Apparatus and method for switching threads in multi-threading processors |
Sep. 2, 2008 |
| 7418575 |
Long instruction word processing with instruction extensions |
Aug. 26, 2008 |
| 7409530 |
Method and apparatus for compressing VLIW instruction and sharing subinstructions |
Aug. 5, 2008 |
| 7406586 |
Fetch and dispatch disassociation apparatus for multi-streaming processors |
Jul. 29, 2008 |
| 7401204 |
Parallel Processor efficiently executing variable instruction word |
Jul. 15, 2008 |
| 7401207 |
Apparatus and method for adjusting instruction thread priority in a multi-thread processor |
Jul. 15, 2008 |
| 7398374 |
Multi-cluster processor for processing instructions of one or more instruction threads |
Jul. 8, 2008 |
| 7395414 |
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions |
Jul. 1, 2008 |
| 7395532 |
Process for running programs on processors and corresponding processor system |
Jul. 1, 2008 |
| 7395413 |
System to dispatch several instructions on available hardware resources |
Jul. 1, 2008 |
| 7395408 |
Parallel execution processor and instruction assigning making use of group number in processing elements |
Jul. 1, 2008 |
| 7380104 |
Method and apparatus for back to back issue of dependent instructions in an out of order issue queue |
May. 27, 2008 |
| 7380107 |
Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss |
May. 27, 2008 |
| 7366884 |
Context switching system for a multi-thread execution pipeline loop and method of operation thereof |
Apr. 29, 2008 |
| 7360062 |
Method and apparatus for selecting an instruction thread for processing in a multi-thread processor |
Apr. 15, 2008 |
| 7353364 |
Apparatus and method for sharing a functional unit execution resource among a plurality of functional units |
Apr. 1, 2008 |
| 7343479 |
Method and apparatus for implementing two architectures in a chip |
Mar. 11, 2008 |
| 7340591 |
Providing parallel operand functions using register file and extra path storage |
Mar. 4, 2008 |
| 7337304 |
Processor for executing instruction control in accordance with dynamic pipeline scheduling and a method thereof |
Feb. 26, 2008 |
| 7308563 |
Dual-target block register allocation |
Dec. 11, 2007 |
| 7278010 |
Instruction execution apparatus comprising a commit stack entry unit |
Oct. 2, 2007 |
| 7269714 |
Inhibiting of a co-issuing instruction in a processor having different pipeline lengths |
Sep. 11, 2007 |
| 7269715 |
Instruction grouping history on fetch-side dispatch group formation |
Sep. 11, 2007 |
| 7266674 |
Programmable delayed dispatch in a multi-threaded pipeline |
Sep. 4, 2007 |
| 7257698 |
Instruction buffer and method of controlling the instruction buffer where buffer entries are issued in a predetermined order |
Aug. 14, 2007 |
| 7254667 |
Data transfer between an external data source and a memory associated with a data processor |
Aug. 7, 2007 |
| 7254689 |
Decompression of block-sorted data |
Aug. 7, 2007 |
| 7240144 |
Arbitration of data transfer requests |
Jul. 3, 2007 |
| 7237095 |
Optimum power efficient shifting algorithm for schedulers |
Jun. 26, 2007 |
| 7237094 |
Instruction group formation and mechanism for SMT dispatch |
Jun. 26, 2007 |
| 7234042 |
Identification bit at a predetermined instruction location that indicates whether the instruction is one or two independent operations and indicates the nature the operations executing in two |
Jun. 19, 2007 |
| 7231510 |
Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof |
Jun. 12, 2007 |
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