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Class Information
Number: 712/214
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction issuing
Description: Subject matter including means or steps for dispatching an instruction for execution (e.g., designating a register after resolving data conflicts).
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620803 |
Data processing device and electronic equipment using pipeline control |
Nov. 17, 2009 |
| 7613904 |
Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler |
Nov. 3, 2009 |
| 7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation |
Oct. 13, 2009 |
| 7594097 |
Microprocessor output ports and control of instructions provided therefrom |
Sep. 22, 2009 |
| 7590824 |
Mixed superscalar and VLIW instruction issuing and processing method and system |
Sep. 15, 2009 |
| 7587717 |
Dynamic master/slave configuration for multiple expansion modules |
Sep. 8, 2009 |
| 7562206 |
Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions |
Jul. 14, 2009 |
| 7552313 |
VLIW digital signal processor for achieving improved binary translation |
Jun. 23, 2009 |
| 7552434 |
Method of performing kernel task upon initial execution of process at user level |
Jun. 23, 2009 |
| 7533248 |
Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor |
May. 12, 2009 |
| 7523295 |
Processor and method of grouping and executing dependent instructions in a packet |
Apr. 21, 2009 |
| 7523297 |
Shadow scan decoder |
Apr. 21, 2009 |
| 7509482 |
Orderly processing ready entries from non-sequentially stored entries using arrival order matrix reordered upon removal of processed entries |
Mar. 24, 2009 |
| 7509483 |
Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors |
Mar. 24, 2009 |
| 7502912 |
Method and apparatus for rescheduling operations in a processor |
Mar. 10, 2009 |
| 7502914 |
Transitive suppression of instruction replay |
Mar. 10, 2009 |
| 7502913 |
Switch prefetch in a multicore computer chip |
Mar. 10, 2009 |
| 7500086 |
Start transactional execution (STE) instruction to support transactional program execution |
Mar. 3, 2009 |
| 7496490 |
Multi-core-model simulation method, multi-core model simulator, and computer product |
Feb. 24, 2009 |
| 7496899 |
Preventing loss of traced information in a data processing apparatus |
Feb. 24, 2009 |
| 7493469 |
Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium |
Feb. 17, 2009 |
| 7493475 |
Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address |
Feb. 17, 2009 |
| 7490219 |
Counter counts valid requests based on a judgment in a system having a plurality of pipeline processors |
Feb. 10, 2009 |
| 7490224 |
Time-of-life counter design for handling instruction flushes from a queue |
Feb. 10, 2009 |
| 7487335 |
Method and apparatus for accessing registers during deferred execution |
Feb. 3, 2009 |
| 7480771 |
Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged |
Jan. 20, 2009 |
| 7478225 |
Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor |
Jan. 13, 2009 |
| 7475225 |
Method and apparatus for microarchitecture partitioning of execution clusters |
Jan. 6, 2009 |
| 7464253 |
Tracking multiple dependent instructions with instruction queue pointer mapping table linked to a multiple wakeup table by a pointer |
Dec. 9, 2008 |
| 7444498 |
Load lookahead prefetch for microprocessors |
Oct. 28, 2008 |
| 7437538 |
Apparatus and method for reducing execution latency of floating point operations having special case operands |
Oct. 14, 2008 |
| 7418576 |
Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operations |
Aug. 26, 2008 |
| 7409530 |
Method and apparatus for compressing VLIW instruction and sharing subinstructions |
Aug. 5, 2008 |
| 7401206 |
Apparatus and method for fine-grained multithreading in a multipipelined processor core |
Jul. 15, 2008 |
| 7395082 |
Method and system for handling events in an application framework for a wireless device |
Jul. 1, 2008 |
| 7392366 |
Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches |
Jun. 24, 2008 |
| 7392367 |
Command ordering among commands in multiple queues using hold-off vector generated from in-use vector and queue dependency scorecard |
Jun. 24, 2008 |
| 7383425 |
Massively reduced instruction set processor |
Jun. 3, 2008 |
| 7380104 |
Method and apparatus for back to back issue of dependent instructions in an out of order issue queue |
May. 27, 2008 |
| 7380105 |
Prediction based instruction steering to wide or narrow integer cluster and narrow address generation |
May. 27, 2008 |
| 7376954 |
Mechanisms for assuring quality of service for programs executing on a multithreaded processor |
May. 20, 2008 |
| 7370176 |
System and method for high frequency stall design |
May. 6, 2008 |
| 7366877 |
Speculative instruction issue in a simultaneously multithreaded processor |
Apr. 29, 2008 |
| 7366878 |
Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching |
Apr. 29, 2008 |
| 7363467 |
Dependence-chain processing using trace descriptors having dependency descriptors |
Apr. 22, 2008 |
| 7363625 |
Method for changing a thread priority in a simultaneous multithread processor |
Apr. 22, 2008 |
| 7360064 |
Thread interleaving in a multithreaded embedded processor |
Apr. 15, 2008 |
| 7350056 |
Method and apparatus for issuing instructions from an issue queue in an information handling system |
Mar. 25, 2008 |
| 7343474 |
Minimal address state in a fine grain multithreaded processor |
Mar. 11, 2008 |
| 7343475 |
Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction |
Mar. 11, 2008 |
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