 |
|
 |
| |
 |
|
Class Information
Number: 712/213
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction decoding (e.g., by microinstruction, start address generator, hardwired) > Predecoding of instruction component
Description: Subject matter for decoding part of an instruction at an earlier processor cycle than the remainder of the instruction.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7590832 |
Information processing device, compressed program producing method, and information processing system |
Sep. 15, 2009 |
| 7509481 |
Patchable and/or programmable pre-decode |
Mar. 24, 2009 |
| 7487334 |
Branch encoding before instruction cache write |
Feb. 3, 2009 |
| 7454597 |
Computer processing system employing an instruction schedule cache |
Nov. 18, 2008 |
| 7447876 |
System and method for handling load and/or store operations in a superscalar microprocessor |
Nov. 4, 2008 |
| 7441104 |
Parallel subword instructions with distributed results |
Oct. 21, 2008 |
| 7415638 |
Pre-decode error handling via branch correction |
Aug. 19, 2008 |
| 7395412 |
Apparatus and method for extending data modes in a microprocessor |
Jul. 1, 2008 |
| 7395414 |
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions |
Jul. 1, 2008 |
| 7376815 |
Methods and apparatus to insure correct predecode |
May. 20, 2008 |
| 7366874 |
Apparatus and method for dispatching very long instruction word having variable length |
Apr. 29, 2008 |
| 7360060 |
Using IMPDEP2 for system commands related to Java accelerator hardware |
Apr. 15, 2008 |
| 7356673 |
System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form |
Apr. 8, 2008 |
| 7346760 |
Data processing apparatus of high speed process using memory of low speed and low power consumption |
Mar. 18, 2008 |
| 7340589 |
Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction |
Mar. 4, 2008 |
| 7334111 |
Method and related device for use in decoding executable code |
Feb. 19, 2008 |
| 7328328 |
Non-temporal memory reference control mechanism |
Feb. 5, 2008 |
| 7321963 |
System and method for storing immediate data |
Jan. 22, 2008 |
| 7305542 |
Instruction length decoder |
Dec. 4, 2007 |
| 7305676 |
Communication device configured for real time processing of user data to be transmitted |
Dec. 4, 2007 |
| 7290081 |
Apparatus and method for implementing a ROM patch using a lockable cache |
Oct. 30, 2007 |
| 7266674 |
Programmable delayed dispatch in a multi-threaded pipeline |
Sep. 4, 2007 |
| 7254697 |
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch |
Aug. 7, 2007 |
| 7246218 |
Systems for increasing register addressing space in instruction-width limited processors |
Jul. 17, 2007 |
| 7237094 |
Instruction group formation and mechanism for SMT dispatch |
Jun. 26, 2007 |
| 7210139 |
Processor cluster architecture and associated parallel processing methods |
Apr. 24, 2007 |
| 7200738 |
Reducing data hazards in pipelined processors to provide high processor utilization |
Apr. 3, 2007 |
| 7197653 |
Microcontroller for fetching and decoding a frequency control signal together with an operation code |
Mar. 27, 2007 |
| 7194602 |
Data processor |
Mar. 20, 2007 |
| 7178046 |
Halting clock signals to input and result latches in processing path upon fetching of instruction not supported |
Feb. 13, 2007 |
| 7174469 |
Processor power and energy management |
Feb. 6, 2007 |
| 7114057 |
System and method for storing immediate data |
Sep. 26, 2006 |
| 7065413 |
Method for producing software for controlling mechanisms and technical systems |
Jun. 20, 2006 |
| 7065215 |
Microprocessor with program and data protection function under multi-task environment |
Jun. 20, 2006 |
| 7007154 |
Method and apparatus for interfacing a processor to a coprocessor |
Feb. 28, 2006 |
| 7003649 |
Control forwarding in a pipeline digital processor |
Feb. 21, 2006 |
| 6988184 |
Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations |
Jan. 17, 2006 |
| 6986024 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
Jan. 10, 2006 |
| 6978233 |
Method for emulating multi-processor environment |
Dec. 20, 2005 |
| 6959375 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
Oct. 25, 2005 |
| 6952754 |
Predecode apparatus, systems, and methods |
Oct. 4, 2005 |
| 6948053 |
Efficiently calculating a branch target address |
Sep. 20, 2005 |
| 6948052 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
Sep. 20, 2005 |
| 6918031 |
Setting condition values in a computer |
Jul. 12, 2005 |
| 6915412 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
Jul. 5, 2005 |
| 6915413 |
Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein |
Jul. 5, 2005 |
| 6883087 |
Processing of binary data for compression |
Apr. 19, 2005 |
| 6880074 |
In-line code suppression |
Apr. 12, 2005 |
| 6877087 |
Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving |
Apr. 5, 2005 |
| 6874078 |
Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit |
Mar. 29, 2005 |
|
|
|
 |
|
 |
|
| |
Randomly Featured Patents |
|
