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Class Information
Number: 712/212
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction decoding (e.g., by microinstruction, start address generator, hardwired) > Decoding by plural parallel decoders
Description: Subject matter including means or steps for decoding an instruction in parallel steps by plural decoding elements.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7496196 |
Method apparatus and system of performing one or more encryption and/or decryption operations |
Feb. 24, 2009 |
| 7478224 |
Microprocessor access of operand stack as a register file using native instructions |
Jan. 13, 2009 |
| 7424594 |
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture |
Sep. 9, 2008 |
| 7366352 |
Method and apparatus for performing fast closest match in pattern recognition |
Apr. 29, 2008 |
| 7340589 |
Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction |
Mar. 4, 2008 |
| 7305542 |
Instruction length decoder |
Dec. 4, 2007 |
| 7289142 |
Monolithic integrated circuit having a number of programmable processing elements |
Oct. 30, 2007 |
| 7243214 |
Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary |
Jul. 10, 2007 |
| 7206921 |
Micro-operation un-lamination |
Apr. 17, 2007 |
| 7180893 |
Parallel layer 2 and layer 3 processing components in a network router |
Feb. 20, 2007 |
| 7143200 |
Semiconductor integrated circuit |
Nov. 28, 2006 |
| 7111151 |
Microprocessor including microcode unit that only changes the value of control signals required for the current cycle operation for reduced power consumption and method therefor |
Sep. 19, 2006 |
| 7103755 |
Apparatus and method for realizing effective parallel execution of instructions in an information processor |
Sep. 5, 2006 |
| 7069555 |
Super-region instruction scheduling and code generation for merging identical instruction into the ready-to-schedule instruction |
Jun. 27, 2006 |
| 7007031 |
Memory system for video decoding system |
Feb. 28, 2006 |
| 6970998 |
Decoding suffix instruction specifying replacement destination for primary instruction |
Nov. 29, 2005 |
| 6968444 |
Microprocessor employing a fixed position dispatch unit |
Nov. 22, 2005 |
| 6959375 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
Oct. 25, 2005 |
| 6944749 |
Method for quickly determining length of an execution package |
Sep. 13, 2005 |
| 6907518 |
Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same |
Jun. 14, 2005 |
| 6904514 |
Data processor |
Jun. 7, 2005 |
| 6889313 |
Selection of decoder output from two different length instruction decoders |
May. 3, 2005 |
| RE38679 |
Data processor and method of processing data |
Dec. 28, 2004 |
| 6820191 |
Apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor |
Nov. 16, 2004 |
| 6766438 |
RISC processor with a debug interface unit |
Jul. 20, 2004 |
| 6745302 |
Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array |
Jun. 1, 2004 |
| 6745319 |
Microprocessor with instructions for shuffling and dealing data |
Jun. 1, 2004 |
| 6745384 |
Anticipatory optimization with composite folding |
Jun. 1, 2004 |
| 6742110 |
Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution |
May. 25, 2004 |
| 6742109 |
Method and apparatus for representing variable-size computer instructions |
May. 25, 2004 |
| 6735685 |
System and method for handling load and/or store operations in a superscalar microprocessor |
May. 11, 2004 |
| 6718457 |
Multiple-thread processor for threaded software applications |
Apr. 6, 2004 |
| 6694426 |
Method and apparatus for staggering execution of a single packed data instruction using the same circuit |
Feb. 17, 2004 |
| 6684322 |
Method and system for instruction length decode |
Jan. 27, 2004 |
| 6678818 |
Decoding next instruction of different length without length mode indicator change upon length change instruction detection |
Jan. 13, 2004 |
| 6647488 |
Processor |
Nov. 11, 2003 |
| 6578136 |
Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder circuit |
Jun. 10, 2003 |
| 6542983 |
Microcomputer/floating point processor interface and method |
Apr. 1, 2003 |
| 6542862 |
Determining register dependency in multiple architecture systems |
Apr. 1, 2003 |
| 6504495 |
Clipping data values in a data processing system |
Jan. 7, 2003 |
| 6499096 |
VLIW processor for exchanging and inputting sub-instructions to containers, and code compression device and method for compressing program code |
Dec. 24, 2002 |
| 6493740 |
Methods and apparatus for multi-thread processing utilizing a single-context architecture |
Dec. 10, 2002 |
| 6484253 |
Data processor |
Nov. 19, 2002 |
| 6460091 |
Address decoding circuit and method for identifying individual addresses and selecting a desired one of a plurality of peripheral macros |
Oct. 1, 2002 |
| 6438680 |
Microprocessor |
Aug. 20, 2002 |
| 6421773 |
Sequence control circuit |
Jul. 16, 2002 |
| 6418528 |
Floating point unit pipeline synchronized with processor pipeline |
Jul. 9, 2002 |
| 6418527 |
Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods |
Jul. 9, 2002 |
| 6408372 |
Data processing control device |
Jun. 18, 2002 |
| 6401194 |
Execution unit for processing a data stream independently and in parallel |
Jun. 4, 2002 |
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