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Class Information
Number: 712/211
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction decoding (e.g., by microinstruction, start address generator, hardwired) > Decoding instruction to generate an address of a microroutine
Description: Subject matter including means or steps for utilizing instruction data to develop a starting or initial address of a microroutine responsible for controlling execution of the instruction.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| RE41012 |
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor |
Nov. 24, 2009 |
| 7617388 |
Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution |
Nov. 10, 2009 |
| 7533250 |
Automatic operand load, modify and store |
May. 12, 2009 |
| 7519799 |
Apparatus having a micro-instruction queue, a micro-instruction pointer programmable logic array and a micro-operation read only memory and method for use thereof |
Apr. 14, 2009 |
| 7506322 |
System and method of utilizing a hardware component to execute an interpretive language |
Mar. 17, 2009 |
| 7502725 |
Method, system and computer program product for register management in a simulation environment |
Mar. 10, 2009 |
| 7500085 |
Identifying code for compilation |
Mar. 3, 2009 |
| 7398372 |
Fusing load and alu operations |
Jul. 8, 2008 |
| 7398376 |
Instructions for ordering execution in pipelined processes |
Jul. 8, 2008 |
| 7321963 |
System and method for storing immediate data |
Jan. 22, 2008 |
| 7290081 |
Apparatus and method for implementing a ROM patch using a lockable cache |
Oct. 30, 2007 |
| 7290120 |
Microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer |
Oct. 30, 2007 |
| 7281121 |
Pipeline processing device and interrupt processing method |
Oct. 9, 2007 |
| 7213126 |
Method and processor including logic for storing traces within a trace cache |
May. 1, 2007 |
| 7191314 |
Reconfigurable CPU with second FSM control unit executing modifiable instructions |
Mar. 13, 2007 |
| 7162621 |
Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration |
Jan. 9, 2007 |
| 7143265 |
Computer program product memory access system |
Nov. 28, 2006 |
| 7139897 |
Computer instruction dispatch |
Nov. 21, 2006 |
| 7114057 |
System and method for storing immediate data |
Sep. 26, 2006 |
| 7111148 |
Method and apparatus for compressing relative addresses |
Sep. 19, 2006 |
| 7107434 |
System, method and apparatus for allocating hardware resources using pseudorandom sequences |
Sep. 12, 2006 |
| 7107439 |
System and method of controlling software decompression through exceptions |
Sep. 12, 2006 |
| 6957319 |
Integrated circuit with multiple microcode ROMs |
Oct. 18, 2005 |
| 6957321 |
Instruction set extension using operand bearing NOP instructions |
Oct. 18, 2005 |
| 6957322 |
Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion |
Oct. 18, 2005 |
| 6880150 |
PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND |
Apr. 12, 2005 |
| 6877069 |
History-based carry predictor for data cache address generation |
Apr. 5, 2005 |
| 6820191 |
Apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor |
Nov. 16, 2004 |
| 6817015 |
Microcontroller with modifiable program |
Nov. 9, 2004 |
| 6789186 |
Method and apparatus to reduce penalty of microcode lookup |
Sep. 7, 2004 |
| 6789185 |
Instruction control apparatus and method using micro program |
Sep. 7, 2004 |
| 6779102 |
Data processor capable of executing an instruction that makes a cache memory ineffective |
Aug. 17, 2004 |
| 6742107 |
Dynamically configured processing of composite stream input data using next conversion determining state transition table searched by converted input data |
May. 25, 2004 |
| 6732258 |
IP relative addressing |
May. 4, 2004 |
| 6711669 |
System and method for storing immediate data |
Mar. 23, 2004 |
| 6691308 |
Method and apparatus for changing microcode to be executed in a processor |
Feb. 10, 2004 |
| 6654875 |
Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator |
Nov. 25, 2003 |
| 6647488 |
Processor |
Nov. 11, 2003 |
| 6618803 |
System and method for finding and validating the most recent advance load for a given checkload |
Sep. 9, 2003 |
| 6618801 |
Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information |
Sep. 9, 2003 |
| 6611909 |
Method and apparatus for dynamically translating program instructions to microcode instructions |
Aug. 26, 2003 |
| 6542981 |
Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode |
Apr. 1, 2003 |
| 6463521 |
Opcode numbering for meta-data encoding |
Oct. 8, 2002 |
| 6457117 |
Processor configured to predecode relative control transfer instructions and replace displacements therein with a target address |
Sep. 24, 2002 |
| 6446190 |
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor |
Sep. 3, 2002 |
| 6442672 |
Method for dynamic allocation and efficient sharing of functional unit datapaths |
Aug. 27, 2002 |
| 6442675 |
Compressed string and multiple generation engine |
Aug. 27, 2002 |
| 6438680 |
Microprocessor |
Aug. 20, 2002 |
| 6412062 |
Injection control mechanism for external events |
Jun. 25, 2002 |
| 6397319 |
Process for executing highly efficient VLIW |
May. 28, 2002 |
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