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Class Information
Number: 712/210
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction decoding (e.g., by microinstruction, start address generator, hardwired) > Decoding instruction to accommodate variable length instruction or operand
Description: Subject matter including means or steps for decoding instruction data whose length varies.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7594098 |
Processes and devices for compression and decompression of executable code by a microprocessor with RISC architecture and related system |
Sep. 22, 2009 |
| 7587535 |
Data transfer control device including endian conversion circuit with data realignment |
Sep. 8, 2009 |
| 7581083 |
Operation processing device, system and method having register-to-register addressing |
Aug. 25, 2009 |
| RE40883 |
Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision |
Aug. 25, 2009 |
| 7581084 |
Method and apparatus for efficient loading and storing of vectors |
Aug. 25, 2009 |
| 7565510 |
Microprocessor with a register selectively storing unaligned load instructions and control method thereof |
Jul. 21, 2009 |
| 7543134 |
Apparatus and method for extending a microprocessor instruction set |
Jun. 2, 2009 |
| 7529912 |
Apparatus and method for instruction-level specification of floating point format |
May. 5, 2009 |
| 7526633 |
Method and system for encoding variable length packets with variable instruction sizes |
Apr. 28, 2009 |
| 7523230 |
Device and method for maximizing performance on a memory interface with a variable number of channels |
Apr. 21, 2009 |
| 7523294 |
Maintaining original per-block number of instructions by inserting NOPs among compressed instructions in compressed block of length compressed by predetermined ratio |
Apr. 21, 2009 |
| 7502911 |
Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length |
Mar. 10, 2009 |
| 7493470 |
Processor apparatus and methods optimized for control applications |
Feb. 17, 2009 |
| 7490118 |
Expanding instruction set using alternate error byte |
Feb. 10, 2009 |
| 7473293 |
Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator |
Jan. 6, 2009 |
| 7454594 |
Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements |
Nov. 18, 2008 |
| 7447871 |
Data access program instruction encoding |
Nov. 4, 2008 |
| RE40498 |
Variable address length compiler and processor improved in address management |
Sep. 9, 2008 |
| 7424597 |
Variable reordering (Mux) instructions for parallel table lookups from registers |
Sep. 9, 2008 |
| 7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers |
Sep. 2, 2008 |
| 7395412 |
Apparatus and method for extending data modes in a microprocessor |
Jul. 1, 2008 |
| 7376814 |
Method for forming variable length instructions in a processing system |
May. 20, 2008 |
| 7373483 |
Mechanism for extending the number of registers in a microprocessor |
May. 13, 2008 |
| 7366876 |
Efficient emulation instruction dispatch based on instruction width |
Apr. 29, 2008 |
| 7360061 |
Program instruction decompression and compression techniques |
Apr. 15, 2008 |
| 7353368 |
Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support |
Apr. 1, 2008 |
| 7343471 |
Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assi |
Mar. 11, 2008 |
| 7343473 |
System and method for translating non-native instructions to native instructions for processing on a host processor |
Mar. 11, 2008 |
| 7340588 |
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code |
Mar. 4, 2008 |
| 7340590 |
Handling register dependencies between instructions specifying different width registers |
Mar. 4, 2008 |
| 7337302 |
Data processing device |
Feb. 26, 2008 |
| 7328328 |
Non-temporal memory reference control mechanism |
Feb. 5, 2008 |
| 7305542 |
Instruction length decoder |
Dec. 4, 2007 |
| 7301541 |
Programmable processor and method with wide operations |
Nov. 27, 2007 |
| 7290120 |
Microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer |
Oct. 30, 2007 |
| 7290153 |
System, method, and apparatus for reducing power consumption in a microprocessor |
Oct. 30, 2007 |
| 7284115 |
Processor which overrides default operand size for implicit stack pointer references and near branches |
Oct. 16, 2007 |
| 7263621 |
System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback |
Aug. 28, 2007 |
| 7254696 |
Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests |
Aug. 7, 2007 |
| 7246218 |
Systems for increasing register addressing space in instruction-width limited processors |
Jul. 17, 2007 |
| 7228403 |
Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture |
Jun. 5, 2007 |
| 7216138 |
Method and apparatus for floating point operations and format conversion operations |
May. 8, 2007 |
| 7216218 |
Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations |
May. 8, 2007 |
| 7213129 |
Method and system for a two stage pipelined instruction decode and alignment using previous instruction length |
May. 1, 2007 |
| 7206921 |
Micro-operation un-lamination |
Apr. 17, 2007 |
| 7197625 |
Alignment and ordering of vector elements for single instruction multiple data processing |
Mar. 27, 2007 |
| 7194602 |
Data processor |
Mar. 20, 2007 |
| 7149879 |
Processor and method of automatic instruction mode switching between n-bit and 2n-bit instructions by using parity check |
Dec. 12, 2006 |
| 7133040 |
System and method for performing an insert-extract instruction |
Nov. 7, 2006 |
| 7120779 |
Address offset generation within a data processing system |
Oct. 10, 2006 |
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