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Class Information
Number: 712/209
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction decoding (e.g., by microinstruction, start address generator, hardwired) > Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)
Description: Subject matter including means or steps for decoding a same instruction identifier to mean a different operation depending on a particular state or condition within the system.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6263421 |
Virtual memory system that is portable between different CPU types |
Jul. 17, 2001 |
| 6260133 |
Processor having operating instruction which uses operation units in different pipelines simultaneously |
Jul. 10, 2001 |
| 6253306 |
Prefetch instruction mechanism for processor |
Jun. 26, 2001 |
| 6253314 |
Instruction set and executing method of the same by microcomputer |
Jun. 26, 2001 |
| 6253307 |
Data processing device with mask and status bits for selecting a set of status conditions |
Jun. 26, 2001 |
| 6237086 |
1 Method to prevent pipeline stalls in superscalar stack based computing systems |
May. 22, 2001 |
| 6233674 |
Method and system for scope-based compression of register and literal encoding in a reduced instruction set computer (RISC) |
May. 15, 2001 |
| 6219776 |
Merged array controller and processing element |
Apr. 17, 2001 |
| 6205540 |
Processor with enhanced instruction set |
Mar. 20, 2001 |
| 6195716 |
System bus interface controlling at least one slave device by exchanging three control signals |
Feb. 27, 2001 |
| 6189087 |
Superscalar instruction decoder including an instruction queue |
Feb. 13, 2001 |
| 6185670 |
System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields |
Feb. 6, 2001 |
| 6178495 |
Processor E-unit to I-unit interface instruction modification with E-unit opcode computer logic in the unit |
Jan. 23, 2001 |
| 6175915 |
Data processor with trie traversal instruction set extension |
Jan. 16, 2001 |
| 6163764 |
Emulation of an instruction set on an instruction set architecture transition |
Dec. 19, 2000 |
| 6163836 |
Processor with programmable addressing modes |
Dec. 19, 2000 |
| 6157997 |
Processor and information processing apparatus with a reconfigurable circuit |
Dec. 5, 2000 |
| 6145078 |
Data processing apparatus and method of starting-up extensions |
Nov. 7, 2000 |
| 6138202 |
Object space manager circuit for obtaining addresses of object headers |
Oct. 24, 2000 |
| 6131154 |
Microcomputer having variable bit width area for displacement |
Oct. 10, 2000 |
| 6128720 |
Distributed processing array with component processors performing customized interpretation of instructions |
Oct. 3, 2000 |
| 6115806 |
Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel |
Sep. 5, 2000 |
| 6105125 |
High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information |
Aug. 15, 2000 |
| 6101592 |
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions |
Aug. 8, 2000 |
| 6093213 |
Flexible implementation of a system management mode (SMM) in a processor |
Jul. 25, 2000 |
| 6088792 |
Avoiding processor serialization after an S/390 SPKA instruction |
Jul. 11, 2000 |
| 6088787 |
Enhanced program counter stack for multi-tasking central processing unit |
Jul. 11, 2000 |
| 6085313 |
Computer processor system for executing RXE format floating point instructions |
Jul. 4, 2000 |
| 6085307 |
Multiple native instruction set master/slave processor arrangement and method thereof |
Jul. 4, 2000 |
| 6079009 |
Coding standard token in a system compromising a plurality of pipeline stages |
Jun. 20, 2000 |
| 6076156 |
Instruction redefinition using model specific registers |
Jun. 13, 2000 |
| 6070236 |
Apparatus for processing a sequence of control commands as well as a method for generating a sequence of control commands, and storage medium for storing control commands |
May. 30, 2000 |
| 6065010 |
Computer implemented method of generating virtual files for sharing information of physical information file |
May. 16, 2000 |
| 6061775 |
Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types |
May. 9, 2000 |
| 6058470 |
Specialized millicode instruction for translate and test |
May. 2, 2000 |
| 6055624 |
Millicode flags with specialized update and branch instructions |
Apr. 25, 2000 |
| 6055623 |
Specialized millicode instruction for editing functions |
Apr. 25, 2000 |
| 6049672 |
Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure |
Apr. 11, 2000 |
| 6038659 |
Method for using read-only memory to generate controls for microprocessor |
Mar. 14, 2000 |
| 6035390 |
Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical |
Mar. 7, 2000 |
| 6031992 |
Combining hardware and software to provide an improved microprocessor |
Feb. 29, 2000 |
| 6026485 |
Instruction folding for a stack-based machine |
Feb. 15, 2000 |
| 6023757 |
Data processor |
Feb. 8, 2000 |
| 6021484 |
Dual instruction set architecture |
Feb. 1, 2000 |
| 6021265 |
Interoperability with multiple instruction sets |
Feb. 1, 2000 |
| 6012138 |
Dynamically variable length CPU pipeline for efficiently executing two instruction sets |
Jan. 4, 2000 |
| 5983337 |
Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction |
Nov. 9, 1999 |
| 5983340 |
Microprocessor system with flexible instruction controlled by prior instruction |
Nov. 9, 1999 |
| 5978899 |
Apparatus and method for parallel processing and self-timed serial marking of variable length instructions |
Nov. 2, 1999 |
| 5964861 |
Method for writing a program to control processors using any instructions selected from original instructions and defining the instructions used as a new instruction set |
Oct. 12, 1999 |
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