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Class Information
Number: 712/209
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction decoding (e.g., by microinstruction, start address generator, hardwired) > Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)
Description: Subject matter including means or steps for decoding a same instruction identifier to mean a different operation depending on a particular state or condition within the system.

Patents under this class:
1 2 3 4 5 6 7 8

Patent Number Title Of Patent Date Issued
7757067 Pre-decoding bytecode prefixes selectively incrementing stack machine program counter Jul. 13, 2010
7752028 Signed/unsigned integer guest compare instructions using unsigned host compare instructions for precise architecture emulation Jul. 6, 2010
7752494 Method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed Jul. 6, 2010
7707389 Multi-ISA instruction fetch unit for a processor, and applications thereof Apr. 27, 2010
7685593 Systems and methods for supporting multiple gaming console emulation environments Mar. 23, 2010
7664934 Data processor decoding instruction formats using operand data Feb. 16, 2010
7664933 Microcomputer and encoding system for instruction code and CPU Feb. 16, 2010
7664765 Method for accelerating the computational speed of a computer algorithm Feb. 16, 2010
7647479 Non-temporal memory reference control mechanism Jan. 12, 2010
7647478 Suppression of store checking Jan. 12, 2010
7631171 Method and apparatus for supporting vector operations on a multi-threaded microprocessor Dec. 8, 2009
7624382 Method and system of control flow graph construction Nov. 24, 2009
7617088 Interpage prologue to protect virtual address mappings Nov. 10, 2009
7613903 Data processing device with instruction translator and memory interface device to translate non-native instructions into native instructions for processor Nov. 3, 2009
7606997 Method and system for using one or more address bits and an instruction to increase an instruction set Oct. 20, 2009
7594098 Processes and devices for compression and decompression of executable code by a microprocessor with RISC architecture and related system Sep. 22, 2009
7590832 Information processing device, compressed program producing method, and information processing system Sep. 15, 2009
7590829 Extension adapter Sep. 15, 2009
7565513 Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations Jul. 21, 2009
7552426 Systems and methods for using synthetic instructions in a virtual machine Jun. 23, 2009
7543287 Using a block device interface to invoke device controller functionality Jun. 2, 2009
7539844 Prefetching indirect array accesses May. 26, 2009
7536682 Method and apparatus for performing interpreter optimizations during program code conversion May. 19, 2009
7536534 Processor capable of being switched among a plurality of operating modes, and method of designing said processor May. 19, 2009
7533250 Automatic operand load, modify and store May. 12, 2009
7529912 Apparatus and method for instruction-level specification of floating point format May. 5, 2009
7526633 Method and system for encoding variable length packets with variable instruction sizes Apr. 28, 2009
7509480 Selection of ISA decoding mode for plural instruction sets based upon instruction address Mar. 24, 2009
7502918 Method and system for data dependent performance increment and power reduction Mar. 10, 2009
7500085 Identifying code for compilation Mar. 3, 2009
7493474 Methods and apparatus for transforming, loading, and executing super-set instructions Feb. 17, 2009
7493479 Method and apparatus for event detection for multiple instruction-set processor Feb. 17, 2009
7478224 Microprocessor access of operand stack as a register file using native instructions Jan. 13, 2009
7473293 Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator Jan. 6, 2009
7467327 Method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed Dec. 16, 2008
7447877 Method and apparatus for converting memory instructions to prefetch operations during a thread switch window Nov. 4, 2008
7447871 Data access program instruction encoding Nov. 4, 2008
7434030 Processor system having accelerator of Java-type of programming language Oct. 7, 2008
7428630 Processor adapted to receive different instruction sets Sep. 23, 2008
7418580 Dynamic object-level code transaction for improved performance of a computer Aug. 26, 2008
7415599 Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location Aug. 19, 2008
7398372 Fusing load and alu operations Jul. 8, 2008
7398373 System and method for processing complex computer instructions Jul. 8, 2008
7363475 Managing registers in a processor to emulate a portion of a stack Apr. 22, 2008
7363476 Method and apparatus to support an expanded register set Apr. 22, 2008
7360060 Using IMPDEP2 for system commands related to Java accelerator hardware Apr. 15, 2008
7353363 Patchable and/or programmable decode using predecode selection Apr. 1, 2008
7353368 Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support Apr. 1, 2008
7340588 Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code Mar. 4, 2008
7301541 Programmable processor and method with wide operations Nov. 27, 2007

1 2 3 4 5 6 7 8

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