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Class Information
Number: 712/208
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction decoding (e.g., by microinstruction, start address generator, hardwired)
Description: Subject matter including an internal hardware, firmware, or software operation by which a computer system determines the meaning of an instruction"s operation code, control bits, and operands.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7590832 |
Information processing device, compressed program producing method, and information processing system |
Sep. 15, 2009 |
| 7571300 |
Modular distributive arithmetic logic unit |
Aug. 4, 2009 |
| 7568083 |
Memory mapped register file and method for accessing the same |
Jul. 28, 2009 |
| 7558942 |
Memory mapped register file and method for accessing the same |
Jul. 7, 2009 |
| 7555421 |
Device emulation for testing data network configurations |
Jun. 30, 2009 |
| 7552316 |
Method and apparatus for compressing instructions to have consecutively addressed operands and for corresponding decompression in a computer system |
Jun. 23, 2009 |
| 7546442 |
Fixed length memory to memory arithmetic and architecture for direct memory access using fixed length instructions |
Jun. 9, 2009 |
| 7533250 |
Automatic operand load, modify and store |
May. 12, 2009 |
| 7529912 |
Apparatus and method for instruction-level specification of floating point format |
May. 5, 2009 |
| 7529914 |
Method and apparatus for speculative execution of uncontended lock instructions |
May. 5, 2009 |
| 7516304 |
Parsing-enhancement facility |
Apr. 7, 2009 |
| 7506322 |
System and method of utilizing a hardware component to execute an interpretive language |
Mar. 17, 2009 |
| 7493473 |
Method of executing instructions using first and second control units that share a state register |
Feb. 17, 2009 |
| 7441098 |
Conditional execution of instructions in a computer |
Oct. 21, 2008 |
| 7441099 |
Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit |
Oct. 21, 2008 |
| 7437532 |
Memory mapped register file |
Oct. 14, 2008 |
| 7434035 |
Method and system for processing instructions in grouped and non-grouped modes |
Oct. 7, 2008 |
| 7430678 |
Low power operation control unit and program optimizing method |
Sep. 30, 2008 |
| 7401176 |
Method and system for fast access to stack memory |
Jul. 15, 2008 |
| 7401204 |
Parallel Processor efficiently executing variable instruction word |
Jul. 15, 2008 |
| 7398355 |
Avoiding locks by transactionally executing critical sections |
Jul. 8, 2008 |
| 7395082 |
Method and system for handling events in an application framework for a wireless device |
Jul. 1, 2008 |
| 7389405 |
Digital signal processor architecture with optimized memory access for code discontinuity |
Jun. 17, 2008 |
| 7383425 |
Massively reduced instruction set processor |
Jun. 3, 2008 |
| 7376813 |
Register move instruction for section select of source operand |
May. 20, 2008 |
| 7376818 |
Program translator and processor |
May. 20, 2008 |
| 7373536 |
Fine granularity halt instruction |
May. 13, 2008 |
| 7367057 |
Processor based system and method for virus detection |
Apr. 29, 2008 |
| 7363476 |
Method and apparatus to support an expanded register set |
Apr. 22, 2008 |
| 7350058 |
Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register |
Mar. 25, 2008 |
| 7346763 |
Processor instruction with repeated execution code |
Mar. 18, 2008 |
| 7343472 |
Processor having a finite field arithmetic unit utilizing an array of multipliers and adders |
Mar. 11, 2008 |
| 7334111 |
Method and related device for use in decoding executable code |
Feb. 19, 2008 |
| 7308320 |
Processor core for using external extended arithmetic unit efficiently and processor incorporating the same |
Dec. 11, 2007 |
| 7302597 |
Microprocessors with improved efficiency processing a variant signed magnitude format |
Nov. 27, 2007 |
| 7301541 |
Programmable processor and method with wide operations |
Nov. 27, 2007 |
| 7293177 |
Preventing virus infection in a computer system |
Nov. 6, 2007 |
| 7290081 |
Apparatus and method for implementing a ROM patch using a lockable cache |
Oct. 30, 2007 |
| 7287149 |
Inserting decoder reconfiguration instruction for routine with limited number of instruction types recoded for reduced bit changes |
Oct. 23, 2007 |
| 7275147 |
Method and apparatus for data alignment and parsing in SIMD computer architecture |
Sep. 25, 2007 |
| 7254689 |
Decompression of block-sorted data |
Aug. 7, 2007 |
| 7251722 |
Semantic processor storage server architecture |
Jul. 31, 2007 |
| 7246218 |
Systems for increasing register addressing space in instruction-width limited processors |
Jul. 17, 2007 |
| 7231508 |
Configurable finite state machine for operation of microinstruction providing execution enable control value |
Jun. 12, 2007 |
| 7231509 |
Extended register bank allocation based on status mask bits set by allocation instruction for respective code block |
Jun. 12, 2007 |
| 7225322 |
Methods of microprocessor instruction result obfuscation |
May. 29, 2007 |
| 7213126 |
Method and processor including logic for storing traces within a trace cache |
May. 1, 2007 |
| 7213129 |
Method and system for a two stage pipelined instruction decode and alignment using previous instruction length |
May. 1, 2007 |
| 7210024 |
Conditional instruction execution via emissary instruction for condition evaluation |
Apr. 24, 2007 |
| 7203935 |
Hardware/software platform for rapid prototyping of code compression technologies |
Apr. 10, 2007 |
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