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Class Information
Number: 712/206
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Instruction fetching > Of multiple instructions simultaneously
Description: Subject matter for causing a fetch of a plurality of instruction data to occur at the same time.

Patents under this class:
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Patent Number Title Of Patent Date Issued
7404042 Handling cache miss in an instruction crossing a cache line boundary Jul. 22, 2008
7404048 Inter-cluster communication module using the memory access network Jul. 22, 2008
7401208 Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor Jul. 15, 2008
7401207 Apparatus and method for adjusting instruction thread priority in a multi-thread processor Jul. 15, 2008
7398374 Multi-cluster processor for processing instructions of one or more instruction threads Jul. 8, 2008
7383403 Concurrent bypass to instruction buffers in a fine grain multithreaded processor Jun. 3, 2008
7373536 Fine granularity halt instruction May. 13, 2008
7366884 Context switching system for a multi-thread execution pipeline loop and method of operation thereof Apr. 29, 2008
7366874 Apparatus and method for dispatching very long instruction word having variable length Apr. 29, 2008
7363625 Method for changing a thread priority in a simultaneous multithread processor Apr. 22, 2008
7363481 Information processing method for controlling the function of a plurality of processors, program for realizing the method, and recording medium Apr. 22, 2008
7360218 System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval Apr. 15, 2008
7360062 Method and apparatus for selecting an instruction thread for processing in a multi-thread processor Apr. 15, 2008
7350030 High performance chipset prefetcher for interleaved channels Mar. 25, 2008
7268787 Dynamic allocation of texture cache memory Sep. 11, 2007
7257807 Method for optimizing execution time of parallel processor programs Aug. 14, 2007
7254689 Decompression of block-sorted data Aug. 7, 2007
7237095 Optimum power efficient shifting algorithm for schedulers Jun. 26, 2007
7234025 Microprocessor with repeat prefetch instruction Jun. 19, 2007
7219185 Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache May. 15, 2007
7194734 Method of executing an interpreter program Mar. 20, 2007
7185178 Fetch speculation in a multithreaded processor Feb. 27, 2007
7143268 Circuit and method for instruction compression and dispersal in wide-issue processors Nov. 28, 2006
7139898 Fetch and dispatch disassociation apparatus for multistreaming processors Nov. 21, 2006
7137109 System and method for managing access to a controlled space in a simulator environment Nov. 14, 2006
7124318 Multiple parallel pipeline processor having self-repairing capability Oct. 17, 2006
7124207 I2O command and status batching Oct. 17, 2006
7124282 Processor architecture with independently addressable memory banks for storing instructions to be executed Oct. 17, 2006
7117343 Fetching instructions to instruction buffer for simultaneous execution with long instruction sensing or buffer overwrite control Oct. 3, 2006
7107433 Mechanism for resource allocation in a digital signal processor based on instruction type information and functional priority and method of operation thereof Sep. 12, 2006
7096466 Loading attribute for partial loading of class files into virtual machines Aug. 22, 2006
7062640 Instruction segment filtering scheme Jun. 13, 2006
7039790 Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit May. 2, 2006
7039791 Instruction cache association crossbar switch May. 2, 2006
7028164 Instruction fetch apparatus for wide issue processors and method of operation Apr. 11, 2006
7000097 System and method for handling load and/or store operations in a superscalar microprocessor Feb. 14, 2006
6981127 Apparatus and method for aligning variable-width instructions with a prefetch buffer Dec. 27, 2005
6976154 Pipelined processor for examining packet header information Dec. 13, 2005
6965987 System and method for handling load and/or store operations in a superscalar microprocessor Nov. 15, 2005
6959375 High-performance, superscalar-based computer system with out-of-order instruction execution Oct. 25, 2005
6957305 Data streaming mechanism in a microprocessor Oct. 18, 2005
6957320 System and method for handling load and/or store operations in a superscalar microprocessor Oct. 18, 2005
6920544 Processor and instruction execution method with reduced address information Jul. 19, 2005
6918018 64-bit single cycle fetch scheme for megastar architecture Jul. 12, 2005
6915412 High-performance, superscalar-based computer system with out-of-order instruction execution Jul. 5, 2005
6898692 Method and apparatus for SIMD processing using multiple queues May. 24, 2005
6898696 Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instruction May. 24, 2005
6898694 High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle May. 24, 2005
6895473 Data control device and an ATM control device May. 17, 2005
6892293 VLIW processor and method therefor May. 10, 2005

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