Resources Contact Us Home
Browse by Category: Main > Information Technology
Class Information
Number: 712/200
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Architecture based instruction processing
Description: Subject matter including instruction data processing for particular processor architectures.

Sub-classes under this class:

Class Number Class Name Patents
712/201 Data flow based system 191
712/203 Multiprocessor instruction 171
712/202 Stack based computer 157

Patents under this class:
1 2 3 4 5 6 7 8 9 10

Patent Number Title Of Patent Date Issued
6112017 Pipeline processing machine having a plurality of reconfigurable processing stages interconnected by a two-wire interface bus Aug. 29, 2000
6092180 Method for measuring latencies by randomly selected sampling of the instructions while the instruction are executed Jul. 18, 2000
6092179 Core processor with customizable function unit Jul. 18, 2000
6092183 Data processor for processing a complex instruction by dividing it into executing units Jul. 18, 2000
6088786 Method and system for coupling a stack based processor to register based functional unit Jul. 11, 2000
6085307 Multiple native instruction set master/slave processor arrangement and method thereof Jul. 4, 2000
6079014 Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state Jun. 20, 2000
6078941 Computational structure having multiple stages wherein each stage includes a pair of adders and a multiplexing circuit capable of operating in parallel Jun. 20, 2000
6055625 Pipeline computer with a scoreboard control circuit to prevent interference between registers Apr. 25, 2000
6052774 Apparatus and method for identifying exception routines indicated by instruction address issued with an instruction fetch command Apr. 18, 2000
6049868 Apparatus for delivering precise traps and interrupts in an out-of-order processor Apr. 11, 2000
6047371 Signal processor for performing conditional operation Apr. 4, 2000
6044223 Object code allocation in multiple systems Mar. 28, 2000
6041402 Direct vectored legacy instruction set emulation Mar. 21, 2000
6038656 Pipelined completion for asynchronous communication Mar. 14, 2000
6038380 Data pipeline system and data encoding method Mar. 14, 2000
6035390 Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical Mar. 7, 2000
6032252 Apparatus and method for efficient loop control in a superscalar microprocessor Feb. 29, 2000
6032246 Bit-slice processing unit having M CPU's reading an N-bit width data element stored bit-sliced across M memories Feb. 29, 2000
6032249 Method and system for executing a serializing instruction while bypassing a floating point unit pipeline Feb. 29, 2000
6023752 Digital data apparatus for transferring data between NTDS and bus topology data buses Feb. 8, 2000
6018776 System for microprogrammable state machine in video parser clearing and resetting processing stages responsive to flush token generating by token generator responsive to received data Jan. 25, 2000
6016539 Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations Jan. 18, 2000
6009509 Method and system for the temporary designation and utilization of a plurality of physical registers as a stack Dec. 28, 1999
6009543 Secure software system and related techniques Dec. 28, 1999
6009263 Emulating agent and method for reformatting computer instructions into a standard uniform format Dec. 28, 1999
6006322 Arithmetic logic unit and microprocessor capable of effectively executing processing for specific application Dec. 21, 1999
6003120 Method and apparatus for performing variable length processor write cycles Dec. 14, 1999
6003038 Object-oriented processor architecture and operating method Dec. 14, 1999
6002880 VLIW processor with less instruction issue slots than functional units Dec. 14, 1999
6000016 Multiported bypass cache in a bypass network Dec. 7, 1999
5996059 System for monitoring an execution pipeline utilizing an address pipeline in parallel with the execution pipeline Nov. 30, 1999
5996063 Management of both renamed and architected registers in a superscalar computer system Nov. 30, 1999
5991874 Conditional move using a compare instruction generating a condition field Nov. 23, 1999
5987592 Flexible resource access in a microprocessor Nov. 16, 1999
5983321 Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache Nov. 9, 1999
5983336 Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to designated execution units groups Nov. 9, 1999
5983339 Power down system and method for pipelined logic functions Nov. 9, 1999
5983340 Microprocessor system with flexible instruction controlled by prior instruction Nov. 9, 1999
5978897 Sequence operation processor employing multi-port RAMs for simultaneously reading and writing Nov. 2, 1999
5978592 Video decompression and decoding system utilizing control and data tokens Nov. 2, 1999
5978896 Method and system for increased instruction dispatch efficiency in a superscalar processor system Nov. 2, 1999
5978899 Apparatus and method for parallel processing and self-timed serial marking of variable length instructions Nov. 2, 1999
5974523 Mechanism for efficiently overlapping multiple operand types in a microprocessor Oct. 26, 1999
5964866 Elastic self-timed interface for data flow elements embodied as selective bypass of stages in an asynchronous microprocessor pipeline Oct. 12, 1999
5966544 Data speculatable processor having reply architecture Oct. 12, 1999
5961632 Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes Oct. 5, 1999
5961633 Execution of data processing instructions Oct. 5, 1999
5961630 Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency Oct. 5, 1999
5956519 Picture end token in a system comprising a plurality of pipeline stages Sep. 21, 1999

1 2 3 4 5 6 7 8 9 10

  Recently Added Patents
Vacuum cleaner
Ultra-wideband communication system and method
Keypoint descriptor generation by complex wavelet analysis
Cosmetic/dermatological compositions comprising naphthoic acid compounds and polyurethane polymers
Selection of a suitable node to host a virtual machine in an environment containing a large number of nodes
Method for manufacturing semiconductor element and semiconductor device, and deposition apparatus
Pyridylphenyl compounds for inflammation and immune-related uses
  Randomly Featured Patents
Method and apparatus for an automated plate handler with elevator and table support mechanism
Method and apparatus for testing the curing characteristics of plastics
Control method for semiconductor manufacturing apparatus, control system for semiconductor manufacturing apparatus, and manufacturing method for semiconductor device
Wire for orthodontic treatment and its manufacturing method
Spacer suitable for use with disk brake including caliper
Restoring virtual devices
Moving picture decoding circuit
Parent unit for babyphone
Device and procedure for the extemporaneous preparation of an individual quantity of sterile liquid
Simultaneous gamma ray measurement of formation bulk density and casing thickness