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Class Information
Number: 712/200
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Architecture based instruction processing
Description: Subject matter including instruction data processing for particular processor architectures.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6044223 |
Object code allocation in multiple systems |
Mar. 28, 2000 |
| 6041402 |
Direct vectored legacy instruction set emulation |
Mar. 21, 2000 |
| 6038656 |
Pipelined completion for asynchronous communication |
Mar. 14, 2000 |
| 6038380 |
Data pipeline system and data encoding method |
Mar. 14, 2000 |
| 6035390 |
Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical |
Mar. 7, 2000 |
| 6032252 |
Apparatus and method for efficient loop control in a superscalar microprocessor |
Feb. 29, 2000 |
| 6032249 |
Method and system for executing a serializing instruction while bypassing a floating point unit pipeline |
Feb. 29, 2000 |
| 6032246 |
Bit-slice processing unit having M CPU's reading an N-bit width data element stored bit-sliced across M memories |
Feb. 29, 2000 |
| 6023752 |
Digital data apparatus for transferring data between NTDS and bus topology data buses |
Feb. 8, 2000 |
| 6018776 |
System for microprogrammable state machine in video parser clearing and resetting processing stages responsive to flush token generating by token generator responsive to received data |
Jan. 25, 2000 |
| 6016539 |
Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations |
Jan. 18, 2000 |
| 6009263 |
Emulating agent and method for reformatting computer instructions into a standard uniform format |
Dec. 28, 1999 |
| 6009509 |
Method and system for the temporary designation and utilization of a plurality of physical registers as a stack |
Dec. 28, 1999 |
| 6009543 |
Secure software system and related techniques |
Dec. 28, 1999 |
| 6006322 |
Arithmetic logic unit and microprocessor capable of effectively executing processing for specific application |
Dec. 21, 1999 |
| 6003120 |
Method and apparatus for performing variable length processor write cycles |
Dec. 14, 1999 |
| 6003038 |
Object-oriented processor architecture and operating method |
Dec. 14, 1999 |
| 6002880 |
VLIW processor with less instruction issue slots than functional units |
Dec. 14, 1999 |
| 6000016 |
Multiported bypass cache in a bypass network |
Dec. 7, 1999 |
| 5996059 |
System for monitoring an execution pipeline utilizing an address pipeline in parallel with the execution pipeline |
Nov. 30, 1999 |
| 5996063 |
Management of both renamed and architected registers in a superscalar computer system |
Nov. 30, 1999 |
| 5991874 |
Conditional move using a compare instruction generating a condition field |
Nov. 23, 1999 |
| 5987592 |
Flexible resource access in a microprocessor |
Nov. 16, 1999 |
| 5983321 |
Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache |
Nov. 9, 1999 |
| 5983339 |
Power down system and method for pipelined logic functions |
Nov. 9, 1999 |
| 5983340 |
Microprocessor system with flexible instruction controlled by prior instruction |
Nov. 9, 1999 |
| 5983336 |
Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to designated execution units groups |
Nov. 9, 1999 |
| 5978592 |
Video decompression and decoding system utilizing control and data tokens |
Nov. 2, 1999 |
| 5978896 |
Method and system for increased instruction dispatch efficiency in a superscalar processor system |
Nov. 2, 1999 |
| 5978897 |
Sequence operation processor employing multi-port RAMs for simultaneously reading and writing |
Nov. 2, 1999 |
| 5978899 |
Apparatus and method for parallel processing and self-timed serial marking of variable length instructions |
Nov. 2, 1999 |
| 5974523 |
Mechanism for efficiently overlapping multiple operand types in a microprocessor |
Oct. 26, 1999 |
| 5964866 |
Elastic self-timed interface for data flow elements embodied as selective bypass of stages in an asynchronous microprocessor pipeline |
Oct. 12, 1999 |
| 5966544 |
Data speculatable processor having reply architecture |
Oct. 12, 1999 |
| 5961630 |
Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency |
Oct. 5, 1999 |
| 5961632 |
Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes |
Oct. 5, 1999 |
| 5961633 |
Execution of data processing instructions |
Oct. 5, 1999 |
| 5956262 |
Digital filtering device |
Sep. 21, 1999 |
| 5956519 |
Picture end token in a system comprising a plurality of pipeline stages |
Sep. 21, 1999 |
| 5956494 |
Method, apparatus, and computer instruction for enabling gain control in a digital signal processor |
Sep. 21, 1999 |
| 5951670 |
Segment register renaming in an out of order processor |
Sep. 14, 1999 |
| 5951674 |
Object-code compatible representation of very long instruction word programs |
Sep. 14, 1999 |
| 5948090 |
Method and apparatus for controlling reset of component boards in a computer system |
Sep. 7, 1999 |
| 5948095 |
Method and apparatus for prefetching data in a computer system |
Sep. 7, 1999 |
| 5937177 |
Control structure for a high-speed asynchronous pipeline |
Aug. 10, 1999 |
| 5931941 |
Interface for a modularized computational unit to a CPU |
Aug. 3, 1999 |
| 5933651 |
Programmable controller |
Aug. 3, 1999 |
| 5928353 |
Clear processing of a translation lookaside buffer with less waiting time |
Jul. 27, 1999 |
| 5928352 |
Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry |
Jul. 27, 1999 |
| 5930495 |
Method and system for processing a first instruction in a first processing environment in response to intiating processing of a second instruction in a emulation environment |
Jul. 27, 1999 |
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