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Class Information
Number: 712/20
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Array processor > Array processor operation > Multimode (e.g., mimd to simd, etc.)
Description: Subject matter wherein the array processor may switch between plural operating modes.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7515899 |
Distributed grid computing method utilizing processing cycles of mobile phones |
Apr. 7, 2009 |
| 7487302 |
Service layer architecture for memory access system and method |
Feb. 3, 2009 |
| 7467286 |
Executing partial-width packed data instructions |
Dec. 16, 2008 |
| 7457938 |
Staggered execution stack for vector processing |
Nov. 25, 2008 |
| 7441098 |
Conditional execution of instructions in a computer |
Oct. 21, 2008 |
| 7418575 |
Long instruction word processing with instruction extensions |
Aug. 26, 2008 |
| 7404066 |
Active memory command engine and method |
Jul. 22, 2008 |
| 7401333 |
Array of parallel programmable processing engines and deterministic method of operating the same |
Jul. 15, 2008 |
| 7392329 |
System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices |
Jun. 24, 2008 |
| 7383427 |
Multi-scalar extension for SIMD instruction set processors |
Jun. 3, 2008 |
| 7360005 |
Software programmable multiple function integrated circuit module |
Apr. 15, 2008 |
| 7313646 |
Interfacing of functional modules in an on-chip system |
Dec. 25, 2007 |
| 7035991 |
Surface computer and computing method using the same |
Apr. 25, 2006 |
| 7028107 |
Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) |
Apr. 11, 2006 |
| 6944744 |
Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor |
Sep. 13, 2005 |
| 6928535 |
Data input/output configuration for transfer among processing elements of different processors |
Aug. 9, 2005 |
| 6925548 |
Data processor assigning the same operation code to multiple operations |
Aug. 2, 2005 |
| 6848041 |
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions |
Jan. 25, 2005 |
| 6839828 |
SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode |
Jan. 4, 2005 |
| 6836837 |
Register addressing |
Dec. 28, 2004 |
| 6785799 |
Multiprocessor with asynchronous pipeline processing of instructions, and control method thereof |
Aug. 31, 2004 |
| 6785800 |
Single instruction stream multiple data stream processor |
Aug. 31, 2004 |
| 6782463 |
Shared memory array |
Aug. 24, 2004 |
| 6775766 |
Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor |
Aug. 10, 2004 |
| 6772368 |
Multiprocessor with pair-wise high reliability mode, and method therefore |
Aug. 3, 2004 |
| 6766437 |
Composite uniprocessor |
Jul. 20, 2004 |
| 6728871 |
Runtime configurable arithmetic and logic cell |
Apr. 27, 2004 |
| 6684318 |
Intermediate-grain reconfigurable processing device |
Jan. 27, 2004 |
| 6643763 |
Register pipe for multi-processing engine environment |
Nov. 4, 2003 |
| 6618698 |
Clustered processors in an emulation engine |
Sep. 9, 2003 |
| 6606699 |
Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit |
Aug. 12, 2003 |
| 6601157 |
Register addressing |
Jul. 29, 2003 |
| 6581152 |
Methods and apparatus for instruction addressing in indirect VLIW processors |
Jun. 17, 2003 |
| 6553479 |
Local control of multiple context processing elements with major contexts and minor contexts |
Apr. 22, 2003 |
| 6526461 |
Interconnect chip for programmable logic devices |
Feb. 25, 2003 |
| 6487651 |
MIMD arrangement of SIMD machines |
Nov. 26, 2002 |
| 6460146 |
System and method for establishing processor redundancy |
Oct. 1, 2002 |
| 6453344 |
Multiprocessor servers with controlled numbered of CPUs |
Sep. 17, 2002 |
| 6453409 |
Digital signal processing system |
Sep. 17, 2002 |
| 6424870 |
Parallel processor |
Jul. 23, 2002 |
| 6404439 |
SIMD control parallel processor with simplified configuration |
Jun. 11, 2002 |
| 6366997 |
Methods and apparatus for manarray PE-PE switch control |
Apr. 2, 2002 |
| 6366998 |
Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model |
Apr. 2, 2002 |
| 6356994 |
Methods and apparatus for instruction addressing in indirect VLIW processors |
Mar. 12, 2002 |
| 6353898 |
Resource management in a clustered computer system |
Mar. 5, 2002 |
| 6351799 |
Integrated circuit for executing software programs |
Feb. 26, 2002 |
| 6347382 |
Multi-port device analysis apparatus and method |
Feb. 12, 2002 |
| 6330657 |
Pairing of micro instructions in the instruction queue |
Dec. 11, 2001 |
| 6321322 |
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions |
Nov. 20, 2001 |
| 6311241 |
Method and configuration for transferring programs |
Oct. 30, 2001 |
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