| Patent Number |
Title Of Patent |
Date Issued |
| 7620678 |
Method and system for reducing the time-to-market concerns for embedded system design |
Nov. 17, 2009 |
| 7606996 |
Array type operation device |
Oct. 20, 2009 |
| 7581080 |
Method for manipulating data in a group of processing elements according to locally maintained counts |
Aug. 25, 2009 |
| 7395082 |
Method and system for handling events in an application framework for a wireless device |
Jul. 1, 2008 |
| 7237086 |
Configuring a management module through a graphical user interface for use in a computer system |
Jun. 26, 2007 |
| 7191312 |
Configurable interconnection of multiple different type functional units array including delay type for different instruction processing |
Mar. 13, 2007 |
| 7155466 |
Policy-based management of a redundant array of independent nodes |
Dec. 26, 2006 |
| 7146405 |
Computer node architecture comprising a dedicated middleware processor |
Dec. 5, 2006 |
| 7100020 |
Digital communications processor |
Aug. 29, 2006 |
| 7058790 |
Cascaded event detection modules for generating combined events interrupt for processor action |
Jun. 6, 2006 |
| 7035991 |
Surface computer and computing method using the same |
Apr. 25, 2006 |
| 6967950 |
Pull transfers and transfer receipt confirmation in a datapipe routing bridge |
Nov. 22, 2005 |
| 6915410 |
Compiler synchronized multi-processor programmable logic device with direct transfer of computation results among processors |
Jul. 5, 2005 |
| 6907513 |
Matrix processing method of shared-memory scalar parallel-processing computer and recording medium |
Jun. 14, 2005 |
| 6836839 |
Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements |
Dec. 28, 2004 |
| 6795909 |
Methods and apparatus for ManArray PE-PE switch control |
Sep. 21, 2004 |
| 6751723 |
Field programmable gate array and microcontroller system-on-a-chip |
Jun. 15, 2004 |
| 6738891 |
Array type processor with state transition controller identifying switch configuration and processing element instruction address |
May. 18, 2004 |
| 6728871 |
Runtime configurable arithmetic and logic cell |
Apr. 27, 2004 |
| 6728862 |
Processor array and parallel data processing methods |
Apr. 27, 2004 |
| 6704313 |
Method of associating forwarding references with data packets by means of a TRIE memory, and packet processing device applying such method |
Mar. 9, 2004 |
| 6658448 |
System and method for assigning processes to specific CPU's to increase scalability and performance of operating systems |
Dec. 2, 2003 |
| 6598146 |
Data-processing arrangement comprising a plurality of processing and memory circuits |
Jul. 22, 2003 |
| 6578133 |
MIMD array of single bit processors for processing logic equations in strict sequential order |
Jun. 10, 2003 |
| 6477697 |
ADDING COMPLEX INSTRUCTION EXTENSIONS DEFINED IN A STANDARDIZED LANGUAGE TO A MICROPROCESSOR DESIGN TO PRODUCE A CONFIGURABLE DEFINITION OF A TARGET INSTRUCTION SET, AND HDL DESCRIPTION OF CIR |
Nov. 5, 2002 |
| 6477636 |
Application-specific integrated circuit for processing defined sequences of assembler instructions |
Nov. 5, 2002 |
| 6366998 |
Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model |
Apr. 2, 2002 |
| 6366997 |
Methods and apparatus for manarray PE-PE switch control |
Apr. 2, 2002 |
| 6351798 |
Address resolution unit and address resolution method for a multiprocessor system |
Feb. 26, 2002 |
| 6324638 |
Processor having vector processing capability and method for executing a vector instruction in a processor |
Nov. 27, 2001 |
| 6308250 |
Method and apparatus for processing a set of data values with plural processing units mask bits generated by other processing units |
Oct. 23, 2001 |
| 6263416 |
Method for reducing number of register file ports in a wide instruction issue processor |
Jul. 17, 2001 |
| 6263415 |
Backup redundant routing system crossbar switch architecture for multi-processor system interconnection networks |
Jul. 17, 2001 |
| 6209077 |
General purpose programmable accelerator board |
Mar. 27, 2001 |
| 6205533 |
Mechanism for efficient data access and communication in parallel computations on an emulated spatial lattice |
Mar. 20, 2001 |
| 6154809 |
Mathematical morphology processing method |
Nov. 28, 2000 |
| 6096091 |
Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip |
Aug. 1, 2000 |
| 6094714 |
Multi-sequential computer for real-time applications |
Jul. 25, 2000 |
| 6049859 |
Image-processing processor |
Apr. 11, 2000 |
| 6041422 |
Fault tolerant memory system |
Mar. 21, 2000 |
| 6038651 |
SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum |
Mar. 14, 2000 |
| 6029001 |
Method of compiling a computer program for performing parallel image processing |
Feb. 22, 2000 |
| 6023742 |
Reconfigurable computing architecture for providing pipelined data paths |
Feb. 8, 2000 |
| 5943502 |
Apparatus and method for fast 1D DCT |
Aug. 24, 1999 |
| 5935216 |
Methods for operating parallel computing systems employing sequenced communications |
Aug. 10, 1999 |
| 5892890 |
Computer system with parallel processor for pixel arithmetic |
Apr. 6, 1999 |
| 5887183 |
Method and system in a data processing system for loading and storing vectors in a plurality of modes |
Mar. 23, 1999 |
| 5848290 |
Data driven information processor |
Dec. 8, 1998 |
| 5838908 |
Device for having processors each having interface for transferring delivery units specifying direction and distance and operable to emulate plurality of field programmable gate arrays |
Nov. 17, 1998 |
| 5838985 |
Parallel processor with memory/ALU inhibiting feature |
Nov. 17, 1998 |
