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Class Information
Number: 712/16
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Array processor > Array processor operation
Description: Subject matter wherein a specific function or process performed by the array processor is specified.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7603541 |
Array synchronization with counters |
Oct. 13, 2009 |
| 7596678 |
Method of shifting data along diagonals in a group of processing elements to transpose the data |
Sep. 29, 2009 |
| 7581079 |
Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions |
Aug. 25, 2009 |
| 7577820 |
Managing data in a parallel processing environment |
Aug. 18, 2009 |
| 7577821 |
IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups |
Aug. 18, 2009 |
| 7574582 |
Processor array including delay elements associated with primary bus nodes |
Aug. 11, 2009 |
| 7574581 |
Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components |
Aug. 11, 2009 |
| 7571300 |
Modular distributive arithmetic logic unit |
Aug. 4, 2009 |
| 7565287 |
Methods and apparatus for efficient vocoder implementations |
Jul. 21, 2009 |
| RE40741 |
System and method for synchronization of video display outputs from multiple PC graphics subsystems |
Jun. 16, 2009 |
| 7536493 |
Method and apparatus for identifying a service processor with current setting information |
May. 19, 2009 |
| 7529917 |
Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array |
May. 5, 2009 |
| 7526630 |
Parallel data processing apparatus |
Apr. 28, 2009 |
| 7515899 |
Distributed grid computing method utilizing processing cycles of mobile phones |
Apr. 7, 2009 |
| 7509442 |
Informational-signal-processing apparatus, functional block, and method of controlling the functional block |
Mar. 24, 2009 |
| 7506134 |
Hardware resource based mapping of cooperative thread arrays (CTA) to result matrix tiles for efficient matrix multiplication in computing system comprising plurality of multiprocessors |
Mar. 17, 2009 |
| 7506297 |
Methodology for scheduling, partitioning and mapping computational tasks onto scalable, high performance, hybrid FPGA networks |
Mar. 17, 2009 |
| 7502915 |
System and method using embedded microprocessor as a node in an adaptable computing machine |
Mar. 10, 2009 |
| 7493475 |
Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address |
Feb. 17, 2009 |
| 7483595 |
Image processing method and device |
Jan. 27, 2009 |
| 7480785 |
Parallel processing device and parallel processing method |
Jan. 20, 2009 |
| 7472392 |
Method for load balancing an n-dimensional array of parallel processing elements |
Dec. 30, 2008 |
| 7461234 |
Loosely-biased heterogeneous reconfigurable arrays |
Dec. 2, 2008 |
| 7457939 |
Processing system with dedicated local memories and busy identification |
Nov. 25, 2008 |
| 7454593 |
Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect |
Nov. 18, 2008 |
| 7451293 |
Array of Boolean logic controlled processing elements with concurrent I/O processing and instruction sequencing |
Nov. 11, 2008 |
| 7451292 |
Methods for transmitting data across quantum interfaces and quantum gates using same |
Nov. 11, 2008 |
| 7447872 |
Inter-chip processor control plane communication |
Nov. 4, 2008 |
| 7441100 |
Processor synchronization in a multi-processor computer system |
Oct. 21, 2008 |
| 7426448 |
Method and apparatus for diagnosing broken scan chain based on leakage light emission |
Sep. 16, 2008 |
| 7418541 |
Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor |
Aug. 26, 2008 |
| 7401333 |
Array of parallel programmable processing engines and deterministic method of operating the same |
Jul. 15, 2008 |
| 7392350 |
Method to operate cache-inhibited memory mapped commands to access registers |
Jun. 24, 2008 |
| 7369683 |
Imaging device |
May. 6, 2008 |
| 7356819 |
Task distribution |
Apr. 8, 2008 |
| 7315933 |
Re-configurable circuit and configuration switching method |
Jan. 1, 2008 |
| 7266255 |
Distributed multi-sample convolution |
Sep. 4, 2007 |
| 7176914 |
System and method for directing the flow of data and instructions into at least one functional unit |
Feb. 13, 2007 |
| 7155466 |
Policy-based management of a redundant array of independent nodes |
Dec. 26, 2006 |
| 7130934 |
Methods and apparatus for providing data transfer control |
Oct. 31, 2006 |
| 7100020 |
Digital communications processor |
Aug. 29, 2006 |
| 7069416 |
Method for forming a single instruction multiple data massively parallel processor system on a chip |
Jun. 27, 2006 |
| 7069557 |
Network processor which defines virtual paths without using logical path descriptors |
Jun. 27, 2006 |
| 7043562 |
Irregular network |
May. 9, 2006 |
| 7028107 |
Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) |
Apr. 11, 2006 |
| 7020761 |
Blocking processing restrictions based on page indices |
Mar. 28, 2006 |
| 6996504 |
Fully scalable computer architecture |
Feb. 7, 2006 |
| 6993764 |
Buffered coscheduling for parallel programming and enhanced fault tolerance |
Jan. 31, 2006 |
| 6990566 |
Multi-channel bi-directional bus network with direction sideband bit for multiple context processing elements |
Jan. 24, 2006 |
| 6967950 |
Pull transfers and transfer receipt confirmation in a datapipe routing bridge |
Nov. 22, 2005 |
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