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Class Information
Number: 712/15
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Array processor > Array processor element interconnection > Reconfiguring
Description: Subject matter wherein an existing structure joining the array processing elements is modified.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7620678 |
Method and system for reducing the time-to-market concerns for embedded system design |
Nov. 17, 2009 |
| 7613899 |
Reconfigurable data processing device and method |
Nov. 3, 2009 |
| 7603540 |
Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration |
Oct. 13, 2009 |
| 7599489 |
Accelerating cryptographic hash computations |
Oct. 6, 2009 |
| 7590821 |
Digital signal processing integrated circuit with I/O connections |
Sep. 15, 2009 |
| 7587613 |
Method and apparatus for selectively enabling a microprocessor-based system |
Sep. 8, 2009 |
| 7577821 |
IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups |
Aug. 18, 2009 |
| 7577727 |
Dynamic multiple cluster system reconfiguration |
Aug. 18, 2009 |
| 7577820 |
Managing data in a parallel processing environment |
Aug. 18, 2009 |
| 7571303 |
Reconfigurable integrated circuit |
Aug. 4, 2009 |
| 7568084 |
Semiconductor integrated circuit including multiple basic cells formed in arrays |
Jul. 28, 2009 |
| 7565525 |
Runtime configurable arithmetic and logic cell |
Jul. 21, 2009 |
| 7543283 |
Flexible instruction processor systems and methods |
Jun. 2, 2009 |
| 7529917 |
Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array |
May. 5, 2009 |
| 7512873 |
Parallel processing apparatus dynamically switching over circuit configuration |
Mar. 31, 2009 |
| 7509479 |
Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit |
Mar. 24, 2009 |
| 7493468 |
Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing |
Feb. 17, 2009 |
| 7489779 |
Hardware implementation of the secure hash standard |
Feb. 10, 2009 |
| 7487302 |
Service layer architecture for memory access system and method |
Feb. 3, 2009 |
| 7484086 |
Data processing apparatus, and method of reconfiguring reconfigurable processing circuit |
Jan. 27, 2009 |
| 7467296 |
Runtime configurable arithmetic and logic cell |
Dec. 16, 2008 |
| 7464251 |
Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements |
Dec. 9, 2008 |
| 7461234 |
Loosely-biased heterogeneous reconfigurable arrays |
Dec. 2, 2008 |
| 7461236 |
Transferring data in a parallel processing environment |
Dec. 2, 2008 |
| 7418579 |
Component with a dynamically reconfigurable architecture |
Aug. 26, 2008 |
| 7418575 |
Long instruction word processing with instruction extensions |
Aug. 26, 2008 |
| 7418574 |
Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction |
Aug. 26, 2008 |
| 7415594 |
Processing system with interspersed stall propagating processors and communication elements |
Aug. 19, 2008 |
| 7408382 |
Configurable circuits, IC's, and systems |
Aug. 5, 2008 |
| 7398380 |
Dynamic hardware partitioning of symmetric multiprocessing systems |
Jul. 8, 2008 |
| 7386704 |
Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method |
Jun. 10, 2008 |
| 7383424 |
Computer architecture containing processor and decoupled coprocessor |
Jun. 3, 2008 |
| 7380100 |
Data processing system and control method utilizing a plurality of date transfer means |
May. 27, 2008 |
| 7379418 |
Method for ensuring system serialization (quiesce) in a multi-processor environment |
May. 27, 2008 |
| 7376811 |
Method and apparatus for performing computations and operations on data using data steering |
May. 20, 2008 |
| 7350054 |
Processor having array of processing elements whose individual operations and mutual connections are variable |
Mar. 25, 2008 |
| 7340585 |
Method and system for fast linked processor in a system on a chip (SoC) |
Mar. 4, 2008 |
| 7325123 |
Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements |
Jan. 29, 2008 |
| 7320062 |
Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements |
Jan. 15, 2008 |
| 7320064 |
Reconfigurable computing architecture for space applications |
Jan. 15, 2008 |
| 7318143 |
Reuseable configuration data |
Jan. 8, 2008 |
| 7305638 |
Method and system for ROM coding to improve yield |
Dec. 4, 2007 |
| 7266672 |
Method and apparatus for retiming in a network of multiple context processing elements |
Sep. 4, 2007 |
| 7237088 |
Methods and apparatus for providing context switching between software tasks with reconfigurable control |
Jun. 26, 2007 |
| 7237087 |
Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells |
Jun. 26, 2007 |
| 7237086 |
Configuring a management module through a graphical user interface for use in a computer system |
Jun. 26, 2007 |
| 7225320 |
Control architecture for a high-throughput multi-processor channel decoding system |
May. 29, 2007 |
| 7210129 |
Method for translating programs for reconfigurable architectures |
Apr. 24, 2007 |
| 7191312 |
Configurable interconnection of multiple different type functional units array including delay type for different instruction processing |
Mar. 13, 2007 |
| 7188192 |
Controlling multiple context processing elements based on transmitted message containing configuration data, address mask, and destination indentification |
Mar. 6, 2007 |
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