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Class Information
Number: 712/14
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Array processor > Array processor element interconnection > Processing element memory
Description: Subject matter which controls the structure joining the memory within an individual array processor element or associated with an individual array processor element.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7584332 |
Computer systems with lightweight multi-threaded architectures |
Sep. 1, 2009 |
| 7581079 |
Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions |
Aug. 25, 2009 |
| 7539845 |
Coupling integrated circuits in a parallel processing environment |
May. 26, 2009 |
| 7519793 |
Facilitating inter-DSP data communications |
Apr. 14, 2009 |
| 7503046 |
Method of obtaining interleave interval for two data values |
Mar. 10, 2009 |
| 7493468 |
Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing |
Feb. 17, 2009 |
| 7461236 |
Transferring data in a parallel processing environment |
Dec. 2, 2008 |
| 7451292 |
Methods for transmitting data across quantum interfaces and quantum gates using same |
Nov. 11, 2008 |
| 7428629 |
Memory request / grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system |
Sep. 23, 2008 |
| 7409529 |
Method and apparatus for a shift register based interconnection for a massively parallel processor array |
Aug. 5, 2008 |
| 7409528 |
Digital signal processing architecture with a wide memory bandwidth and a memory mapping method thereof |
Aug. 5, 2008 |
| 7404066 |
Active memory command engine and method |
Jul. 22, 2008 |
| 7398368 |
Atomic operation involving processors with different memory transfer operation sizes |
Jul. 8, 2008 |
| 7386689 |
Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner |
Jun. 10, 2008 |
| 7370046 |
Sort processing method and sort processing apparatus |
May. 6, 2008 |
| 7369683 |
Imaging device |
May. 6, 2008 |
| 7363304 |
Method and system for providing a hardware sort for a large number of items |
Apr. 22, 2008 |
| 7325122 |
Facilitating inter-DSP data communications |
Jan. 29, 2008 |
| 7272691 |
Interconnect switch assembly with input and output ports switch coupling to processor or memory pair and to neighbor ports coupling to adjacent pairs switch assemblies |
Sep. 18, 2007 |
| 7237087 |
Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells |
Jun. 26, 2007 |
| 7181593 |
Active memory command engine and method |
Feb. 20, 2007 |
| 7149876 |
Method and apparatus for a shift register based interconnection for a massively parallel processor array |
Dec. 12, 2006 |
| 7100020 |
Digital communications processor |
Aug. 29, 2006 |
| 7072357 |
Flexible buffering scheme for multi-rate SIMD processor |
Jul. 4, 2006 |
| 7069416 |
Method for forming a single instruction multiple data massively parallel processor system on a chip |
Jun. 27, 2006 |
| 7065215 |
Microprocessor with program and data protection function under multi-task environment |
Jun. 20, 2006 |
| 7058540 |
Method and system for accelerating power complementary cumulative distribution function measurements |
Jun. 6, 2006 |
| 7020764 |
Semiconductor processing device |
Mar. 28, 2006 |
| 7010668 |
Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution |
Mar. 7, 2006 |
| 6986020 |
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller |
Jan. 10, 2006 |
| 6967950 |
Pull transfers and transfer receipt confirmation in a datapipe routing bridge |
Nov. 22, 2005 |
| 6912626 |
Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner |
Jun. 28, 2005 |
| 6901491 |
Method and apparatus for integration of communication links with a remote direct memory access protocol |
May. 31, 2005 |
| 6839648 |
Systems for providing zero latency, non-modulo looping and branching of test pattern data for automatic test equipment |
Jan. 4, 2005 |
| 6795909 |
Methods and apparatus for ManArray PE-PE switch control |
Sep. 21, 2004 |
| 6775667 |
Method and system for providing a hardware sort for a large number of items |
Aug. 10, 2004 |
| 6760831 |
Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution |
Jul. 6, 2004 |
| 6754803 |
Multiprocessor system and address solution method of the same |
Jun. 22, 2004 |
| 6754801 |
Method and apparatus for a shift register based interconnection for a massively parallel processor array |
Jun. 22, 2004 |
| 6754802 |
Single instruction multiple data massively parallel processor systems on a chip and system using same |
Jun. 22, 2004 |
| 6732068 |
Memory circuit for use in hardware emulation system |
May. 4, 2004 |
| 6728863 |
Wide connections for transferring data between PE's of an N-dimensional mesh-connected SIMD array while transferring operands from memory |
Apr. 27, 2004 |
| 6728862 |
Processor array and parallel data processing methods |
Apr. 27, 2004 |
| 6728841 |
Conserving system memory bandwidth during a memory read operation in a multiprocessing computer system |
Apr. 27, 2004 |
| 6711665 |
Associative processor |
Mar. 23, 2004 |
| 6662246 |
Two-dimensional memory access in image processing systems |
Dec. 9, 2003 |
| 6654646 |
Enhanced memory addressing control |
Nov. 25, 2003 |
| 6609235 |
Method for providing a fill pattern for an integrated circuit design |
Aug. 19, 2003 |
| 6606589 |
Disk storage subsystem with internal parallel data path and non-volatile memory |
Aug. 12, 2003 |
| 6591357 |
Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements |
Jul. 8, 2003 |
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