| Patent Number |
Title Of Patent |
Date Issued |
| 7581087 |
Method and apparatus for debugging a multicore system |
Aug. 25, 2009 |
| 7574581 |
Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components |
Aug. 11, 2009 |
| 7526631 |
Data processing system with backplane and processor books configurable to support both technical and commercial workloads |
Apr. 28, 2009 |
| 7441098 |
Conditional execution of instructions in a computer |
Oct. 21, 2008 |
| 7185226 |
Fault tolerance in a supercomputer through dynamic repartitioning |
Feb. 27, 2007 |
| 7103639 |
Method and apparatus for processing unit synchronization for scalable parallel processing |
Sep. 5, 2006 |
| 7043562 |
Irregular network |
May. 9, 2006 |
| 6973559 |
Scalable hypercube multiprocessor network for massive parallel processing |
Dec. 6, 2005 |
| 6898657 |
Autonomous signal processing resource for selective series processing of data in transit on communications paths in multi-processor arrangements |
May. 24, 2005 |
| 6873287 |
Signal processing arrangement |
Mar. 29, 2005 |
| 6769056 |
Methods and apparatus for manifold array processing |
Jul. 27, 2004 |
| 6754892 |
Instruction packing for an advanced microprocessor |
Jun. 22, 2004 |
| 6754735 |
Single descriptor scatter gather data transfer to or from a host processor |
Jun. 22, 2004 |
| 6741552 |
Fault-tolerant, highly-scalable cell switching architecture |
May. 25, 2004 |
| 6680915 |
Distributed computing system using virtual buses and data communication method for the same |
Jan. 20, 2004 |
| 6609189 |
Cycle segmented prefix circuits |
Aug. 19, 2003 |
| 6598145 |
Irregular network |
Jul. 22, 2003 |
| 6526375 |
Self-configuring store-and-forward computer network |
Feb. 25, 2003 |
| 6510539 |
System and method for physically modeling electronic modules wiring |
Jan. 21, 2003 |
| 6487456 |
Method and apparatus for creating a selectable electrical characteristic |
Nov. 26, 2002 |
| 6470441 |
Methods and apparatus for manifold array processing |
Oct. 22, 2002 |
| 6418427 |
Online modifications of dimension structures in multidimensional processing |
Jul. 9, 2002 |
| 6356900 |
Online modifications of relations in multidimensional processing |
Mar. 12, 2002 |
| 6230252 |
Hybrid hypercube/torus architecture |
May. 8, 2001 |
| 6219775 |
Massively parallel computer including auxiliary vector processor |
Apr. 17, 2001 |
| 6195738 |
Combined associative processor and random access memory architecture |
Feb. 27, 2001 |
| 6167502 |
Method and apparatus for manifold array processing |
Dec. 26, 2000 |
| RE36954 |
SIMD system having logic units arranged in stages of tree structure and operation of stages controlled through respective control registers |
Nov. 14, 2000 |
| 6128719 |
Indirect rotator graph network |
Oct. 3, 2000 |
| 6038688 |
Node disjoint path forming method for hypercube having damaged node |
Mar. 14, 2000 |
| 5991866 |
Method and system for generating a program to facilitate rearrangement of address bits among addresses in a massively parallel processor system |
Nov. 23, 1999 |
| 5963745 |
APAP I/O programmable router |
Oct. 5, 1999 |
| 5887184 |
Method and apparatus for partitioning an interconnection medium in a partitioned multiprocessor computer system |
Mar. 23, 1999 |
| 5842034 |
Two dimensional crossbar mesh for multi-processor interconnect |
Nov. 24, 1998 |
| 5826033 |
Parallel computer apparatus and method for performing all-to-all communications among processing elements |
Oct. 20, 1998 |
| 5822605 |
Parallel processor system with a broadcast message serializing circuit provided within a network |
Oct. 13, 1998 |
| 5794059 |
N-dimensional modified hypercube |
Aug. 11, 1998 |
| 5740463 |
Information processing system and method of computation performed with an information processing system |
Apr. 14, 1998 |
| 5689722 |
Multipipeline multiprocessor system |
Nov. 18, 1997 |
| 5675823 |
Grain structured processing architecture device and a method for processing three dimensional volume element data |
Oct. 7, 1997 |
| 5669008 |
Hierarchical fat hypercube architecture for parallel processing systems |
Sep. 16, 1997 |
| 5642524 |
Methods for generating N-dimensional hypercube structures and improved such structures |
Jun. 24, 1997 |
| 5617577 |
Advanced parallel array processor I/O connection |
Apr. 1, 1997 |
| 5598570 |
Efficient data allocation management in multiprocessor computer system |
Jan. 28, 1997 |
| 5560027 |
Scalable parallel processing systems wherein each hypernode has plural processing modules interconnected by crossbar and each processing module has SCI circuitry for forming multi-dimensional |
Sep. 24, 1996 |
| 5430885 |
Multi-processor system and co-processor used for the same |
Jul. 4, 1995 |
| 5430887 |
Cube-like processor array architecture |
Jul. 4, 1995 |
| 5420982 |
Hyper-cube network control system having different connection patterns corresponding to phase signals for interconnecting inter-node links and between input/output links |
May. 30, 1995 |
| 5379440 |
Parallel processor with array of clustered processing elements having inputs seperate from outputs and outputs limited to a maximum of two per dimension |
Jan. 3, 1995 |
| 5367692 |
Parallel computer system including efficient arrangement for performing communications among processing node to effect an array transposition operation |
Nov. 22, 1994 |
