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Class Information
Number: 712/11
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Array processor > Array processor element interconnection
Description: Subject matter including details of a structure which mutually joins the identical processing elements.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7602423 |
Integrated circuit for a digital camera system |
Oct. 13, 2009 |
| 7599998 |
Message handling communication between a source processor core and destination processor cores |
Oct. 6, 2009 |
| 7595659 |
Logic cell array and bus system |
Sep. 29, 2009 |
| 7594060 |
Data buffer allocation in a non-blocking data services platform using input/output switching fabric |
Sep. 22, 2009 |
| 7590821 |
Digital signal processing integrated circuit with I/O connections |
Sep. 15, 2009 |
| 7581079 |
Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions |
Aug. 25, 2009 |
| 7581081 |
Systems and methods for software extensible multi-processing |
Aug. 25, 2009 |
| 7577820 |
Managing data in a parallel processing environment |
Aug. 18, 2009 |
| 7565287 |
Methods and apparatus for efficient vocoder implementations |
Jul. 21, 2009 |
| 7539845 |
Coupling integrated circuits in a parallel processing environment |
May. 26, 2009 |
| 7526631 |
Data processing system with backplane and processor books configurable to support both technical and commercial workloads |
Apr. 28, 2009 |
| 7515899 |
Distributed grid computing method utilizing processing cycles of mobile phones |
Apr. 7, 2009 |
| 7508776 |
Controlling method and device for data transmission |
Mar. 24, 2009 |
| 7502844 |
Abnormality indicator of a desired group of resource elements |
Mar. 10, 2009 |
| 7503046 |
Method of obtaining interleave interval for two data values |
Mar. 10, 2009 |
| 7477608 |
Methods for routing packets on a linear array of processors |
Jan. 13, 2009 |
| 7471643 |
Loosely-biased heterogeneous reconfigurable arrays |
Dec. 30, 2008 |
| 7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor |
Dec. 30, 2008 |
| 7461234 |
Loosely-biased heterogeneous reconfigurable arrays |
Dec. 2, 2008 |
| 7461236 |
Transferring data in a parallel processing environment |
Dec. 2, 2008 |
| 7454593 |
Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect |
Nov. 18, 2008 |
| 7451292 |
Methods for transmitting data across quantum interfaces and quantum gates using same |
Nov. 11, 2008 |
| 7444276 |
Hardware acceleration system for logic simulation using shift register as local cache |
Oct. 28, 2008 |
| 7418536 |
Processor having systolic array pipeline for processing data packets |
Aug. 26, 2008 |
| 7406075 |
Crossbar switch, method for controlling operation thereof, and program for controlling operation thereof |
Jul. 29, 2008 |
| 7406582 |
Resolving crossing requests in multi-node configurations |
Jul. 29, 2008 |
| 7386689 |
Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner |
Jun. 10, 2008 |
| 7383242 |
Computer-implemented method and apparatus for item processing |
Jun. 3, 2008 |
| 7379418 |
Method for ensuring system serialization (quiesce) in a multi-processor environment |
May. 27, 2008 |
| 7356669 |
Processing system and method for transmitting data |
Apr. 8, 2008 |
| 7337249 |
I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures |
Feb. 26, 2008 |
| 7315934 |
Data processor and program for processing a data matrix |
Jan. 1, 2008 |
| 7308558 |
Multiprocessor data processing system having scalable data interconnect and data routing mechanism |
Dec. 11, 2007 |
| 7302548 |
System and method for communicating in a multi-processor environment |
Nov. 27, 2007 |
| 7299339 |
Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework |
Nov. 20, 2007 |
| 7275145 |
Processing element with next and previous neighbor registers for direct data transfer |
Sep. 25, 2007 |
| 7263602 |
Programmable pipeline fabric utilizing partially global configuration buses |
Aug. 28, 2007 |
| 7263597 |
Network device including dedicated resources control plane |
Aug. 28, 2007 |
| 7243175 |
I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures |
Jul. 10, 2007 |
| 7203816 |
Multi-processor system apparatus allowing a compiler to conduct a static scheduling process over a large scale system of processors and memory modules |
Apr. 10, 2007 |
| 7197624 |
Manifold array processor |
Mar. 27, 2007 |
| 7185174 |
Switch complex selectively coupling input and output of a node in two-dimensional array to four ports and using four switches coupling among ports |
Feb. 27, 2007 |
| 7185175 |
Configurable bi-directional bus for communicating between autonomous units |
Feb. 27, 2007 |
| 7181594 |
Context pipelines |
Feb. 20, 2007 |
| 7176914 |
System and method for directing the flow of data and instructions into at least one functional unit |
Feb. 13, 2007 |
| 7171499 |
Processor surrogate for use in multiprocessor systems and multiprocessor system using same |
Jan. 30, 2007 |
| 7098437 |
Semiconductor integrated circuit device having a plurality of photo detectors and processing elements |
Aug. 29, 2006 |
| 7069372 |
Processor having systolic array pipeline for processing data packets |
Jun. 27, 2006 |
| 7065672 |
Apparatus and methods for fault-tolerant computing using a switching fabric |
Jun. 20, 2006 |
| 7051185 |
Hypercomputer |
May. 23, 2006 |
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