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Class Information
Number: 712/10
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Array processor
Description: Subject matter comprising four or more identical processing elements (e.g., cells) joined in a two-dimensional or higher arrangement.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6122747 |
Intelligent subsystem interface for modular hardware system |
Sep. 19, 2000 |
| 6122724 |
Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation |
Sep. 19, 2000 |
| 6108763 |
Simultaneous parity generating/reading circuit for massively parallel processing systems |
Aug. 22, 2000 |
| 6105102 |
Mechanism for minimizing overhead usage of a host system by polling for subsequent interrupts after service of a prior interrupt |
Aug. 15, 2000 |
| 6100992 |
Image-forming system |
Aug. 8, 2000 |
| 6085275 |
Data processing system and method thereof |
Jul. 4, 2000 |
| 6055605 |
Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches |
Apr. 25, 2000 |
| 6047115 |
Method for configuring FPGA memory planes for virtual hardware computation |
Apr. 4, 2000 |
| 6038688 |
Node disjoint path forming method for hypercube having damaged node |
Mar. 14, 2000 |
| 6035374 |
Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency |
Mar. 7, 2000 |
| 6023753 |
Manifold array processor |
Feb. 8, 2000 |
| 6023742 |
Reconfigurable computing architecture for providing pipelined data paths |
Feb. 8, 2000 |
| 5995977 |
Module configuration systems, methods and computer program products for data processing systems |
Nov. 30, 1999 |
| 5991866 |
Method and system for generating a program to facilitate rearrangement of address bits among addresses in a massively parallel processor system |
Nov. 23, 1999 |
| 5987587 |
Single chip multiprocessor with shared execution units |
Nov. 16, 1999 |
| 5983327 |
Data path architecture and arbitration scheme for providing access to a shared system resource |
Nov. 9, 1999 |
| 5966528 |
SIMD/MIMD array processor with vector processing |
Oct. 12, 1999 |
| 5963745 |
APAP I/O programmable router |
Oct. 5, 1999 |
| 5958028 |
GPIB system and method which allows multiple thread access to global variables |
Sep. 28, 1999 |
| 5944811 |
Superscalar processor with parallel issue and execution device having forward map of operand and instruction dependencies |
Aug. 31, 1999 |
| 5930519 |
Distributed branch logic system and method for a geometry accelerator |
Jul. 27, 1999 |
| 5925114 |
Modem implemented in software for operation on a general purpose computer having operating system with different execution priority levels |
Jul. 20, 1999 |
| 5898881 |
Parallel computer system with error status signal and data-driven processor |
Apr. 27, 1999 |
| 5892962 |
FPGA-based processor |
Apr. 6, 1999 |
| 5892961 |
Field programmable gate array having programming instructions in the configuration bitstream |
Apr. 6, 1999 |
| 5890203 |
Data transfer device for transfer of data distributed and stored by striping |
Mar. 30, 1999 |
| 5887138 |
Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes |
Mar. 23, 1999 |
| 5887165 |
Dynamically reconfigurable hardware system for real-time control of processes |
Mar. 23, 1999 |
| 5859981 |
Method for deadlock-free message passing in MIMD systems using routers and buffers |
Jan. 12, 1999 |
| 5850564 |
Scalable multiple level tab oriented interconnect architecture |
Dec. 15, 1998 |
| 5822604 |
Method of optimizing recognition of collective data movement in a parallel distributed system |
Oct. 13, 1998 |
| 5812825 |
Integrated console and console apparatus and method for use thereof |
Sep. 22, 1998 |
| 5812852 |
Software implemented method for thread-privatizing user-specified global storage objects in parallel computer programs via program transformation |
Sep. 22, 1998 |
| 5794059 |
N-dimensional modified hypercube |
Aug. 11, 1998 |
| 5748942 |
Efficient three-dimensional layout method for logic cell arrays |
May. 5, 1998 |
| 5734921 |
Advanced parallel array processor computer package |
Mar. 31, 1998 |
| 5732211 |
Advanced data server having a plurality of rings connected to a server controller which controls the rings to cause them to receive and store data and/or retrieve and read out data |
Mar. 24, 1998 |
| 5694602 |
Weighted system and method for spatial allocation of a parallel load |
Dec. 2, 1997 |
| 5652907 |
High speed mask and logical combination operations for parallel processor units |
Jul. 29, 1997 |
| 5586258 |
Multilevel hierarchical multiprocessor computer system |
Dec. 17, 1996 |
| 5551039 |
Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements |
Aug. 27, 1996 |
| 5535406 |
Virtual processor module including a reconfigurable programmable matrix |
Jul. 9, 1996 |
| 5535393 |
System for parallel processing that compiles a filed sequence of instructions within an iteration space |
Jul. 9, 1996 |
| 5438682 |
Data processing system for rewriting parallel processor output data using a sequential processor |
Aug. 1, 1995 |
| 5367677 |
System for iterated generation from an array of records of a posting file with row segments based on column entry value ranges |
Nov. 22, 1994 |
| 5325464 |
Pyramid learning architecture neurocomputer |
Jun. 28, 1994 |
| 5287466 |
Method and apparatus for parallel loads equalizing utilizing instruction sorting by columns based on predicted instruction execution time |
Feb. 15, 1994 |
| 5287532 |
Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte |
Feb. 15, 1994 |
| 4933895 |
Cellular array having data dependent processing capabilities |
Jun. 12, 1990 |
| 4799152 |
Pipeline feedback array sorter with multi-string sort array and merge tree array |
Jan. 17, 1989 |
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