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Class Information
Number: 712/10
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) > Processing architecture > Array processor
Description: Subject matter comprising four or more identical processing elements (e.g., cells) joined in a two-dimensional or higher arrangement.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6735684 |
Parallel-processing apparatus and method |
May. 11, 2004 |
| 6718514 |
Parity checking device and method in data communication system |
Apr. 6, 2004 |
| 6711724 |
Semiconductor integrated circuit device having pipeline stage and designing method therefor |
Mar. 23, 2004 |
| 6681341 |
Processor isolation method for integrated multi-processor systems |
Jan. 20, 2004 |
| 6662246 |
Two-dimensional memory access in image processing systems |
Dec. 9, 2003 |
| 6658448 |
System and method for assigning processes to specific CPU's to increase scalability and performance of operating systems |
Dec. 2, 2003 |
| 6657632 |
Unified memory distributed across multiple nodes in a computer graphics system |
Dec. 2, 2003 |
| 6631466 |
Parallel string pattern searches in respective ones of array of nanocomputers |
Oct. 7, 2003 |
| 6625721 |
Registers for 2-D matrix processing |
Sep. 23, 2003 |
| 6625722 |
Processor controller for accelerating instruction issuing rate |
Sep. 23, 2003 |
| 6622233 |
Hypercomputer |
Sep. 16, 2003 |
| 6606704 |
Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode |
Aug. 12, 2003 |
| 6606699 |
Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit |
Aug. 12, 2003 |
| 6581152 |
Methods and apparatus for instruction addressing in indirect VLIW processors |
Jun. 17, 2003 |
| 6567837 |
Object oriented processor arrays |
May. 20, 2003 |
| 6560629 |
Multi-thread processing |
May. 6, 2003 |
| 6557094 |
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions |
Apr. 29, 2003 |
| 6526461 |
Interconnect chip for programmable logic devices |
Feb. 25, 2003 |
| 6523101 |
Installed-software development assistance system |
Feb. 18, 2003 |
| 6484065 |
DRAM enhanced processor |
Nov. 19, 2002 |
| 6467009 |
Configurable processor system unit |
Oct. 15, 2002 |
| 6460127 |
Apparatus and method for signal processing |
Oct. 1, 2002 |
| 6457073 |
Methods and apparatus for providing data transfer control |
Sep. 24, 2002 |
| 6449664 |
Two dimensional direct memory access in image processing systems |
Sep. 10, 2002 |
| 6414368 |
Microcomputer with high density RAM on single chip |
Jul. 2, 2002 |
| 6415286 |
Computer system and computerized method for partitioning data for parallel processing |
Jul. 2, 2002 |
| 6405299 |
Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity |
Jun. 11, 2002 |
| 6405301 |
Parallel data processing |
Jun. 11, 2002 |
| 6393504 |
Dynamic address mapping and redundancy in a modular memory device |
May. 21, 2002 |
| 6370634 |
Data flow computer with two switches |
Apr. 9, 2002 |
| 6349391 |
Redundant clock system and method for use in a computer |
Feb. 19, 2002 |
| 6321322 |
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions |
Nov. 20, 2001 |
| 6317819 |
Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction |
Nov. 13, 2001 |
| 6311311 |
Multiple input shift register (MISR) signatures used on architected registers to detect interim functional errors on instruction stream test |
Oct. 30, 2001 |
| 6308279 |
Method and apparatus for power mode transition in a multi-thread processor |
Oct. 23, 2001 |
| 6308251 |
Reduced power parallel processor apparatus |
Oct. 23, 2001 |
| 6272620 |
Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation |
Aug. 7, 2001 |
| 6260082 |
Methods and apparatus for providing data transfer control |
Jul. 10, 2001 |
| 6230251 |
File replication methods and apparatus for reducing port pressure in a clustered processor |
May. 8, 2001 |
| 6219777 |
Register file having shared and local data word parts |
Apr. 17, 2001 |
| 6219775 |
Massively parallel computer including auxiliary vector processor |
Apr. 17, 2001 |
| 6216174 |
System and method for fast barrier synchronization |
Apr. 10, 2001 |
| 6209077 |
General purpose programmable accelerator board |
Mar. 27, 2001 |
| 6205532 |
Apparatus and methods for connecting modules using remote switching |
Mar. 20, 2001 |
| 6192384 |
System and method for performing compound vector operations |
Feb. 20, 2001 |
| 6173386 |
Parallel processor with debug capability |
Jan. 9, 2001 |
| 6173389 |
Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor |
Jan. 9, 2001 |
| 6148399 |
Advanced instrument controller statement of government interest |
Nov. 14, 2000 |
| 6145072 |
Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same |
Nov. 7, 2000 |
| 6122724 |
Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation |
Sep. 19, 2000 |
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