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Class Information
Number: 712
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) >
Description: This class provides, within a computer or digital data processing system, for subject matter represented by a particular arrangement that includes at least one of the following means: A) components of an individual complete processor, which may be formed on a single integrated circuit (IC); B) components of a complete digital data processing system; C) plural processors; or D) plural digital data processing systems; wherein the particular arrangement further includes at least one of the following functions:










Class Number Class Name No. of Patents
712/200

Architecture based instruction processing

487
712/201

Data flow based system

191
712/203

Multiprocessor instruction

171
712/202

Stack based computer

157
712/300

Byte-word rearranging, bit-field insertion or extraction, string length detecting, or sequence detecting

379
712/216

Dynamic instruction dependency checking, monitoring or conflict resolution

762
712/218

Commitment control or register bypass

594
712/219

Reducing an impact of a stall or pipeline bubble

441
712/217

Scoreboarding, reservation station, or aliasing

612
712/204

Instruction alignment

247
712/208

Instruction decoding (e.g., by microinstruction, start address generator, hardwired)

491
712/212

Decoding by plural parallel decoders

232
712/209

Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)

361
712/210

Decoding instruction to accommodate variable length instruction or operand

496
712/211

Decoding instruction to generate an address of a microroutine

174
712/213

Predecoding of instruction component

309
712/205

Instruction fetching

395
712/206

Of multiple instructions simultaneously

269
712/207

Prefetching

630
712/214

Instruction issuing

437
712/215

Simultaneous issuance of multiple instructions

612
712/1

Processing architecture

469
712/10

Array processor

345
712/11

Array processor element interconnection

480
712/12

Cube or hypercube

90
712/13

Partitioning

202
712/14

Processing element memory

182
712/15

Reconfiguring

358
712/16

Array processor operation

281
712/17

Application specific

117
712/18

Data flow array processor

127
712/20

Multimode (e.g., mimd to simd, etc.)

181
712/21

Multiple instruction, multiple data (mimd)

104
712/22

Single instruction, multiple data (simd)

467
712/19

Systolic array processor

66
712/25

Data driven or demand driven processor

135
712/26

Detection/pairing based on destination, id tag, or data

91
712/27

Particular data driven memory structure

70
712/28

Distributed processing system

477
712/29

Interface

218
712/30

Operation

186
712/31

Master/slave

150
712/24

Long instruction word

338
712/32

Microprocessor or multichip or multimodule processor having sequential program control

544
712/36

Application specific

334
712/33

Having multiple internal buses

169
712/34

Including coprocessor

425
712/35

Digital signal processor

293
712/38

Offchip interface

203
712/40

External sync or interrupt signal

82
712/39

Externally controlled internal mode switching via pin

82
712/42

Operation

169
712/43

Mode switching

293
712/37

Programmable (e.g., eprom)

236
712/41

Risc

158
712/23

Superscalar

762
712/2

Vector processor

146
712/6

Controlling access to external vector data

80
712/4

Distributing of vector data to vector registers

156
712/5

Masking to control an access to data in vector register

81
712/3

Scalar/vector processor interface

84
712/7

Vector processor operation

150
712/9

Concurrent

100
712/8

Sequential

49
712/220

Processing control

786
712/221

Arithmetic operation instruction processing

419
712/222

Floating point or vector

358
712/233

Branching (e.g., delayed branch, loop control, branch predict, interrupt)

439
712/234

Conditional branching

417
712/239

Branch prediction

576
712/240

History table

364
712/236

Evaluation of multiple conditions or multiway branching

155
712/237

Prefetching a branch target (i.e., look ahead)

356
712/238

Branch target buffer

230
712/235

Simultaneous parallel fetching or executing of both branch and fall-through path

192
712/244

Exeception processing (e.g., interrupts and traps)

743
712/241

Loop execution

323
712/242

To macro-instruction routine

115
712/243

To microinstruction subroutine

107
712/228

Context preserving (e.g., context swapping, checkpointing, register windowing

816
712/231

Detecting end or completion of microprogram

62
712/230

Generating next microinstruction address

101
712/232

Hardwired controller

39
712/226

Instruction modification based on condition

456
712/223

Logic operation instruction processing

240
712/224

Masking

179
712/229

Mode switch or change

504
712/225

Processing control for data transfer

880
712/245

Processing sequence control (i.e., microsequencing)

545
712/247

Multilevel microcontroller (e.g., dual-level control store)

62
712/246

Plural microsequencers (e.g., dual microsequencers)

36
712/248

Writable/changeable control store architecture

179
712/227

Specialized instruction processing in support of testing, debugging, emulation

818
 
 
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