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Class Information
Number: 712
Name: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) >
Description: This class provides, within a computer or digital data processing system, for subject matter represented by a particular arrangement that includes at least one of the following means: A) components of an individual complete processor, which may be formed on a single integrated circuit (IC); B) components of a complete digital data processing system; C) plural processors; or D) plural digital data processing systems; wherein the particular arrangement further includes at least one of the following functions:

Class Number	Class Name	No. of Patents
712/200	Architecture based instruction processing	424
712/201	Data flow based system	156
712/203	Multiprocessor instruction	134
712/202	Stack based computer	140
712/300	Byte-word rearranging, bit-field insertion or extraction, string length detecting, or sequence detecting	316
712/216	Dynamic instruction dependency checking, monitoring or conflict resolution	566
712/218	Commitment control or register bypass	505
712/219	Reducing an impact of a stall or pipeline bubble	351
712/217	Scoreboarding, reservation station, or aliasing	528
712/204	Instruction alignment	222
712/208	Instruction decoding (e.g., by microinstruction, start address generator, hardwired)	381
712/212	Decoding by plural parallel decoders	211
712/209	Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)	299
712/210	Decoding instruction to accommodate variable length instruction or operand	427
712/211	Decoding instruction to generate an address of a microroutine	157
712/213	Predecoding of instruction component	267
712/205	Instruction fetching	298
712/206	Of multiple instructions simultaneously	230
712/207	Prefetching	508
712/214	Instruction issuing	300
712/215	Simultaneous issuance of multiple instructions	505
712/1	Processing architecture	375
712/10	Array processor	204
712/11	Array processor element interconnection	368
712/12	Cube or hypercube	65
712/13	Partitioning	152
712/14	Processing element memory	156
712/15	Reconfiguring	232
712/16	Array processor operation	199
712/17	Application specific	82
712/18	Data flow array processor	108
712/20	Multimode (e.g., mimd to simd, etc.)	138
712/21	Multiple instruction, multiple data (mimd)	79
712/22	Single instruction, multiple data (simd)	314
712/19	Systolic array processor	52
712/25	Data driven or demand driven processor	115
712/26	Detection/pairing based on destination, id tag, or data	83
712/27	Particular data driven memory structure	62
712/28	Distributed processing system	301
712/29	Interface	155
712/30	Operation	117
712/31	Master/slave	101
712/24	Long instruction word	289
712/32	Microprocessor or multichip or multimodule processor having sequential program control	422
712/36	Application specific	287
712/33	Having multiple internal buses	143
712/34	Including coprocessor	319
712/35	Digital signal processor	249
712/38	Offchip interface	188
712/40	External sync or interrupt signal	71
712/39	Externally controlled internal mode switching via pin	75
712/42	Operation	160
712/43	Mode switching	240
712/37	Programmable (e.g., eprom)	205
712/41	Risc	141
712/23	Superscalar	723
712/2	Vector processor	112
712/6	Controlling access to external vector data	72
712/4	Distributing of vector data to vector registers	130
712/5	Masking to control an access to data in vector register	68
712/3	Scalar/vector processor interface	58
712/7	Vector processor operation	101
712/9	Concurrent	81
712/8	Sequential	43
712/220	Processing control	403
712/221	Arithmetic operation instruction processing	329
712/222	Floating point or vector	277
712/233	Branching (e.g., delayed branch, loop control, branch predict, interrupt)	338
712/234	Conditional branching	338
712/239	Branch prediction	446
712/240	History table	287
712/236	Evaluation of multiple conditions or multiway branching	124
712/237	Prefetching a branch target (i.e., look ahead)	315
712/238	Branch target buffer	195
712/235	Simultaneous parallel fetching or executing of both branch and fall-through path	155
712/244	Exeception processing (e.g., interrupts and traps)	558
712/241	Loop execution	254
712/242	To macro-instruction routine	99
712/243	To microinstruction subroutine	98
712/228	Context preserving (e.g., context swapping, checkpointing, register windowing	595
712/231	Detecting end or completion of microprogram	56
712/230	Generating next microinstruction address	97
712/232	Hardwired controller	31
712/226	Instruction modification based on condition	353
712/223	Logic operation instruction processing	204
712/224	Masking	153
712/229	Mode switch or change	358
712/225	Processing control for data transfer	590
712/245	Processing sequence control (i.e., microsequencing)	510
712/247	Multilevel microcontroller (e.g., dual-level control store)	57
712/246	Plural microsequencers (e.g., dual microsequencers)	35
712/248	Writable/changeable control store architecture	172
712/227	Specialized instruction processing in support of testing, debugging, emulation	623