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Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory

Patents under this class:

Patent Number Title Of Patent Date Issued
7725641 Memory array structure and single instruction multiple data processor including the same and methods thereof May. 25, 2010
7721130 Apparatus and method for switching an apparatus to a power saving mode May. 18, 2010
7721066 Efficient encoding for detecting load dependency on store with misalignment May. 18, 2010
7721011 Method and apparatus for reordering memory accesses to reduce power consumption in computer systems May. 18, 2010
7716392 Computer system having an I/O module directly connected to a main storage for DMA transfer May. 11, 2010
7707388 Computer memory architecture for hybrid serial and parallel computing systems Apr. 27, 2010
7707366 Memory control device Apr. 27, 2010
7707363 Multi-port memory architecture for storing multi-dimensional arrays II Apr. 27, 2010
7707355 Memory system for selectively transmitting command and address signals Apr. 27, 2010
7707351 Methods and systems for an identifier-based memory section Apr. 27, 2010
7702883 Variable-width memory Apr. 20, 2010
7702880 Hybrid mapping implementation within a non-volatile memory system Apr. 20, 2010
7702834 Data transmission method serial bus system and switch-on unit for a passive station Apr. 20, 2010
7697515 On-line data migration of a logical/virtual storage array Apr. 13, 2010
7697363 Memory device having data input and output ports and memory module and memory system including the same Apr. 13, 2010
7694193 Systems and methods for implementing a stride value for accessing memory Apr. 6, 2010
7694109 Data processing apparatus of high speed process using memory of low speed and low power consumption Apr. 6, 2010
7694093 Memory module and method for mirroring data by rank Apr. 6, 2010
7689981 Mobile handset with efficient interruption point detection during a multiple-pass update process Mar. 30, 2010
7685354 Multiple-core processor with flexible mapping of processor cores to cache banks Mar. 23, 2010
7681023 Method for ensuring optimal memory configuration in a computer Mar. 16, 2010
7673103 Logging of level-two cache transactions into banks of the level-two cache stores the transactions for diagnostic and debug Mar. 2, 2010
7673094 Memory devices with buffered command address bus Mar. 2, 2010
7673093 Computer system having daisy chained memory chips Mar. 2, 2010
7664922 Data transfer arbitration apparatus and data transfer arbitration method Feb. 16, 2010
7664905 Page stream sorter for poor locality access patterns Feb. 16, 2010
7660951 Atomic read/write support in a multi-module memory configuration Feb. 9, 2010
7660940 Carrier having daisy chain of self timed memory chips Feb. 9, 2010
7653448 NICAM processing method Jan. 26, 2010
7650457 Memory module comprising a plurality of memory devices Jan. 19, 2010
7647470 Memory device and controlling method for elongating the life of nonvolatile memory Jan. 12, 2010
7640386 Systems and methods for providing memory modules with multiple hub devices Dec. 29, 2009
7640366 Storage controller to control access to storage device via serial communication unit by executing control step units Dec. 29, 2009
7636833 Method for selecting memory busses according to physical memory organization information associated with virtual address translation tables Dec. 22, 2009
7636808 Semiconductor device Dec. 22, 2009
7631152 Determining memory flush states for selective heterogeneous memory flushes Dec. 8, 2009
7631138 Adaptive mode switching of flash memory address mapping based on host usage characteristics Dec. 8, 2009
7627712 Method and system for managing multi-plane memory devices Dec. 1, 2009
7627711 Memory controller for daisy chained memory chips Dec. 1, 2009
7624310 System and method for initializing a memory system, and memory device and processor-based system using same Nov. 24, 2009
7620793 Mapping memory partitions to virtual memory pages Nov. 17, 2009
7620784 High speed nonvolatile memory device using parallel writing among a plurality of interfaces Nov. 17, 2009
7617367 Memory system including a two-on-one link memory subsystem interconnection Nov. 10, 2009
7617356 Refresh port for a dynamic memory Nov. 10, 2009
7617350 Carrier having daisy chained memory chips Nov. 10, 2009
7613866 Method for controlling access to a multibank memory Nov. 3, 2009
7609562 Configurable device ID in non-volatile memory Oct. 27, 2009
7594088 System and method for an asynchronous data buffer having buffer write and read pointers Sep. 22, 2009
7587559 Systems and methods for memory module power management Sep. 8, 2009
7587545 Shared memory device Sep. 8, 2009

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