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Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory

Patents under this class:

Patent Number Title Of Patent Date Issued
6324628 Programming flash in a closed system Nov. 27, 2001
6324630 Method of processing a data move instruction for moving data between main storage and extended storage and data move instruction processing apparatus Nov. 27, 2001
6321239 Efficient volume copy using pre-configuration of log structured target storage Nov. 20, 2001
6321290 Program checking method, program checking apparatus, and computer-readable recording medium for recording target program checking program capable of reducing tracing interrupt time Nov. 20, 2001
6321316 Method and apparatus for local control signal generation in a memory device Nov. 20, 2001
6317857 System and method for utilizing checksums to recover data Nov. 13, 2001
6314489 Methods and systems for storing cell data using a bank of cell buffers Nov. 6, 2001
6310875 Method and apparatus for port memory multicast common memory switches Oct. 30, 2001
6301636 Content addressable memory system with cascaded memories and self timed signals Oct. 9, 2001
6301649 Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions Oct. 9, 2001
6297857 Method for accessing banks of DRAM Oct. 2, 2001
6298413 Apparatus for controlling refresh of a multibank memory device Oct. 2, 2001
6298426 Controller configurable for use with multiple memory organizations Oct. 2, 2001
6298437 Method for vectoring pread/pwrite system calls Oct. 2, 2001
6295575 Configuring vectors of logical storage units for data storage partitioning and sharing Sep. 25, 2001
6292867 Data processing system Sep. 18, 2001
6289397 Disk drive or like peripheral storage device adapted for firmware upgrading, self-testing, etc. Sep. 11, 2001
6289411 Circuit for generating a chip-enable signal for a multiple chip configuration Sep. 11, 2001
6289429 Accessing multiple memories using address conversion among multiple addresses Sep. 11, 2001
6286075 Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than M Sep. 4, 2001
6282603 Memory with pipelined accessed and priority precharge Aug. 28, 2001
6282604 Memory controller and method for meory devices with mutliple banks of memory cells Aug. 28, 2001
6275894 Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture Aug. 14, 2001
6275895 Memory refreshing system Aug. 14, 2001
6272594 Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes Aug. 7, 2001
6272610 File memory device using flash memories, and an information processing system using the same Aug. 7, 2001
6266733 Two-level mini-block storage system for volume data sets Jul. 24, 2001
6266734 Reducing memory latency by not performing bank conflict checks on idle banks Jul. 24, 2001
6266735 Information processing system Jul. 24, 2001
6266762 Information processing apparatus Jul. 24, 2001
6263399 Microprocessor to NAND flash interface Jul. 17, 2001
6260101 Microcontroller having dedicated hardware for memory address space expansion supporting both static and dynamic memory devices Jul. 10, 2001
6260127 Method and apparatus for supporting heterogeneous memory in computer systems Jul. 10, 2001
6256725 Shared datapath processor utilizing stack-based and register-based storage spaces Jul. 3, 2001
6253226 Duration-based memory management of complex objects Jun. 26, 2001
6253276 Apparatus for adaptive decoding of memory addresses Jun. 26, 2001
6253277 Memory system having flexible addressing and method using tag and data bus communication Jun. 26, 2001
6253278 Synchronous DRAM modules including multiple clock out signals for increasing processing speed Jun. 26, 2001
6247070 Pipelined packet-oriented memory system having a undirectional command and address bus and a bidirectional data bus Jun. 12, 2001
6247095 Digital reverberation processor and method for generating digital reverberation Jun. 12, 2001
6233650 Using FET switches for large memory arrays May. 15, 2001
6233651 Programmable FIFO memory scheme May. 15, 2001
6233652 Translation lookaside buffer for multiple page sizes May. 15, 2001
6233658 Memory write and read control May. 15, 2001
6233662 Method and apparatus for interleaving memory across computer memory banks May. 15, 2001
6230236 Content addressable memory system with cascaded memories and self timed signals May. 8, 2001
6230244 Memory device with read access controlled by code May. 8, 2001
6226707 System and method for arranging, accessing and distributing data to achieve zero cycle penalty for access crossing a cache line May. 1, 2001
6226726 Memory bank organization correlating distance with a memory map May. 1, 2001
6219746 Data processing system having a synchronous memory with an output circuit which selectively outputs groups of M data bits Apr. 17, 2001

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