Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Browse by Category: Main > Information Technology
Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory










Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Next

Patent Number Title Of Patent Date Issued
6425044 Apparatus for providing fast memory decode using a bank conflict table Jul. 23, 2002
6425045 Reducing memory latency by not performing bank conflict checks on idle banks Jul. 23, 2002
6415353 Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same Jul. 2, 2002
6415363 Memory statistics counter and method for counting the number of accesses to a portion of memory Jul. 2, 2002
6415366 Method and apparatus for load distribution across memory banks with constrained access Jul. 2, 2002
6412039 Cross-bank, cross-page data accessing and controlling system Jun. 25, 2002
6405286 Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes Jun. 11, 2002
6401160 Method and apparatus to permit adjustable code/data boundary in a nonvolatile memory Jun. 4, 2002
6401161 High speed bus interface for non-volatile integrated circuit memory supporting continuous transfer Jun. 4, 2002
6401162 Generalized fourier transform processing system Jun. 4, 2002
6401180 Bank history table for improved pre-charge scheduling of random access memory banks Jun. 4, 2002
6396729 Memory system having flexible bus structure and method May. 28, 2002
6397314 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices May. 28, 2002
6393512 Circuit and method for detecting bank conflicts in accessing adjacent banks May. 21, 2002
6393534 Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory May. 21, 2002
6393541 Data transfer memory having the function of transferring data on a system bus May. 21, 2002
6389520 Method for controlling out of order accessing to a multibank memory May. 14, 2002
6385692 Methods and apparatus for variable length SDRAM transfers May. 7, 2002
6385746 Memory test circuit May. 7, 2002
6381668 Address mapping for system memory Apr. 30, 2002
6381669 Multi-bank, fault-tolerant, high-performance memory addressing system and method Apr. 30, 2002
6381685 Dynamic configuration of memory module using presence detect data Apr. 30, 2002
6381686 Parallel processor comprising multiple sub-banks to which access requests are bypassed from a request queue when corresponding page faults are generated Apr. 30, 2002
6378018 Memory device and system including a low power interface Apr. 23, 2002
6378032 Bank conflict avoidance in multi-bank DRAMS with shared sense amplifiers Apr. 23, 2002
6374323 Computer memory conflict avoidance using page registers Apr. 16, 2002
6374326 Multiple bank CAM architecture and method for performing concurrent lookup operations Apr. 16, 2002
6370610 Apparatus for swapping input values into corresponding output values Apr. 9, 2002
6366980 Disc drive for achieving improved audio and visual data transfer Apr. 2, 2002
6366983 Method and system for symmetric memory population Apr. 2, 2002
RE37613 System for specifying addresses by creating a multi-bit ranked ordered anchor pattern and creating next address by shifting in the direction of the superior position Mar. 26, 2002
6360285 Apparatus for determining memory bank availability in a computer system Mar. 19, 2002
6360292 Method and system for processing pipelined memory commands Mar. 19, 2002
6360305 Method and apparatus for optimizing memory performance with opportunistic pre-charging Mar. 19, 2002
6356986 Method and apparatus for analyzing a main memory configuration Mar. 12, 2002
6356988 Memory access system, address converter, and address conversion method capable of reducing a memory access time Mar. 12, 2002
6353571 Memory system having flexible bus structure and method Mar. 5, 2002
6351787 File memory device and information processing apparatus using the same Feb. 26, 2002
6347354 Apparatus and method for maximizing information transfers over limited interconnect resources Feb. 12, 2002
6347365 Data storage system having a[n] memory responsive to clock pulses produced on a bus and clock pulses produced by an internal clock Feb. 12, 2002
6347366 System and method for automatically optimizing software performance Feb. 12, 2002
6345348 Memory system capable of supporting different memory devices and a memory device used therefor Feb. 5, 2002
6343046 Semiconductor integrated circuit device Jan. 29, 2002
6340973 Memory control unit and memory control method and medium containing program for realizing the same Jan. 22, 2002
6339809 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers Jan. 15, 2002
6339817 Semiconductor memory including main and sub memory portions having plural memory cell groups and a bidirectional data transfer circuit Jan. 15, 2002
6336166 Memory control device with split read for ROM access Jan. 1, 2002
6330637 Synchronous DRAM modules including multiple clock out signals for increasing processing speed Dec. 11, 2001
6330650 Data receiver that performs synchronous data transfer with reference to memory module Dec. 11, 2001
6327606 Memory management of complex objects returned from procedure calls Dec. 4, 2001

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Next










 
 
  Recently Added Patents
Smart television system having methods or means for accessing paid or subscribed digital content from the internet
Sulfonated amorphous carbon, process for producing the same and use thereof
Method and system and policy server for guaranteeing data not to be interrupted
Pet urn enclosure
Communication network management system, method and program, and management computer
Image display device and method of changing first EDID with second EDID wherein the second EDID information is compatible with image display device
Display screen with graphical user interface
  Randomly Featured Patents
Self-cooled loudspeaker
Apparatus for supporting a test specimen for compression testing
Range hood fire suppression system with visible status indication
Rod holder adapter
Apparatus and method for defining laser cleave alignment
Radio interface
Flexible, region-selectable inherently de-coupled sandwiched solenoidal array coil
Gate drive circuit for thyristor deflection system
Fracturing method for stimulation of wells utilizing carbon dioxide based fluids
Inverter control circuit