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Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory










Patents under this class:
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Patent Number Title Of Patent Date Issued
6532525 Method and apparatus for accessing memory Mar. 11, 2003
6530007 Method and apparatus for supporting heterogeneous memory in computer systems Mar. 4, 2003
6526471 Method and apparatus for a high-speed memory subsystem Feb. 25, 2003
6526473 Memory module system for controlling data input and output by connecting selected memory modules to a data line Feb. 25, 2003
6523018 Neural chip architecture and neural networks incorporated therein Feb. 18, 2003
6523060 Method and apparatus for the management of queue pointers by multiple processors in a digital communications network Feb. 18, 2003
6523089 Memory controller with power management logic Feb. 18, 2003
6519673 Multi-bank, fault-tolerant, high-performance memory addressing system and method Feb. 11, 2003
6515936 Memory system having flexible bus structure and method Feb. 4, 2003
6513106 Mirror addressing in a DSP Jan. 28, 2003
6510486 Clocking scheme for independently reading and writing multiple width words from a memory array Jan. 21, 2003
6507884 Microcomputer with multiple memories for storing data Jan. 14, 2003
6507885 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure Jan. 14, 2003
6507886 Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory Jan. 14, 2003
6507900 Semiconductor memory device including plural blocks with selecting and sensing or reading operations in different blocks carried out in parallel Jan. 14, 2003
6505282 Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing character Jan. 7, 2003
6502161 Memory system including a point-to-point linked memory subsystem Dec. 31, 2002
6502162 Configuring vectors of logical storage units for data storage partitioning and sharing Dec. 31, 2002
6502173 System for accessing memory and method therefore Dec. 31, 2002
6499094 Management of memory heap space for data files accessible to programs operating in different addressing modes Dec. 24, 2002
6493793 Content addressable memory device having selective cascade logic and method for selectively combining match information in a CAM device Dec. 10, 2002
6493815 Interleaving/deinterleaving device and method for communication system Dec. 10, 2002
6487140 Circuit for managing the transfer of data streams from a plurality of sources within a system Nov. 26, 2002
6483755 Memory modules with high speed latched sense amplifiers Nov. 19, 2002
6480938 Efficient I-cache structure to support instructions crossing line boundaries Nov. 12, 2002
6477614 Method for implementing multiple memory buses on a memory module Nov. 5, 2002
6477630 Hierarchical row activation method for banking control in multi-bank DRAM Nov. 5, 2002
6470414 Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture Oct. 22, 2002
6470431 Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data Oct. 22, 2002
6467013 Memory transceiver to couple an additional memory channel to an existing memory channel Oct. 15, 2002
6467015 High speed bus interface for non-volatile integrated circuit memory supporting continuous transfer Oct. 15, 2002
6467018 Method and apparatus for addressing individual banks of DRAMs on a memory card Oct. 15, 2002
6463500 Apparatus and method to access computer memory by processing object data as sub-object and shape parameter Oct. 8, 2002
6457094 Memory array architecture supporting block write operation Sep. 24, 2002
6457110 Method of accessing syncronous dynamic random access memory in scanner Sep. 24, 2002
6453380 Address mapping for configurable memory system Sep. 17, 2002
6449681 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers Sep. 10, 2002
6445825 Apparatus and method of generating compressed data Sep. 3, 2002
6446157 Cache bank conflict avoidance and cache collision avoidance Sep. 3, 2002
6446158 Memory system using FET switches to select memory banks Sep. 3, 2002
6446163 Memory card with signal processing element Sep. 3, 2002
6446183 Systems and methods for persistent and robust memory management Sep. 3, 2002
6446184 Address re-mapping for memory module using presence detect data Sep. 3, 2002
6442667 Selectively powering X Y organized memory banks Aug. 27, 2002
6438641 Information processing apparatus using index and tag addresses for cache access Aug. 20, 2002
6434679 Architecture for vital data management in a multi-module machine and process for implementing an architecture of this type Aug. 13, 2002
6430647 Data processing system for use in conjunction with a font card or the like Aug. 6, 2002
6430648 Arranging address space to access multiple memory banks Aug. 6, 2002
6430672 Method for performing address mapping using two lookup tables Aug. 6, 2002
6425043 Method for providing fast memory decode using a bank conflict table Jul. 23, 2002

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