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Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory










Patents under this class:
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Patent Number Title Of Patent Date Issued
6633965 Memory controller with 1.times./M.times. read capability Oct. 14, 2003
6631427 Data recording apparatus and method including control data invalidating function Oct. 7, 2003
6629194 Method and apparatus for low power memory bit line precharge Sep. 30, 2003
6629219 Method and apparatus for providing highly programmable memory mapping and improved interleaving Sep. 30, 2003
6629225 Method and apparatus for control calibration of multiple memory modules within a memory channel Sep. 30, 2003
6625685 Memory controller with programmable configuration Sep. 23, 2003
6622196 Method of controlling semiconductor memory device having memory areas with different capacities Sep. 16, 2003
6622225 System for minimizing memory bank conflicts in a computer system Sep. 16, 2003
6622230 Multi-set block erase Sep. 16, 2003
6611894 Data retrieval apparatus Aug. 26, 2003
6609174 Embedded MRAMs including dual read ports Aug. 19, 2003
6606673 Direct memory access transfer apparatus Aug. 12, 2003
6606680 Method and apparatus for accessing banked embedded dynamic random access memory devices Aug. 12, 2003
6604165 Library control device for logically dividing and controlling library device and method thereof Aug. 5, 2003
6604166 Memory architecture for parallel data access along any given dimension of an n-dimensional rectangular data array Aug. 5, 2003
6604180 Pipelined memory controller Aug. 5, 2003
6601130 Memory interface unit with programmable strobes to select different memory devices Jul. 29, 2003
6598112 Method and apparatus for executing a program using primary, secondary and tertiary memories Jul. 22, 2003
6591323 Memory controller with arbitration among several strobe requests Jul. 8, 2003
6591330 System and method for flexible flash file Jul. 8, 2003
6591349 Mechanism to reorder memory read and write transactions for reduced latency and increased bandwidth Jul. 8, 2003
6587912 Method and apparatus for implementing multiple memory buses on a memory module Jul. 1, 2003
6587913 Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode Jul. 1, 2003
6587934 Memory controller and data processing system Jul. 1, 2003
6581133 Reclaiming memory from deleted applications Jun. 17, 2003
6574700 Semiconductor device with auto address allocation means for a cache memory Jun. 3, 2003
6571310 Method and apparatus for managing a heterogeneous data storage system May. 27, 2003
6571323 Memory-access management method and system for synchronous dynamic Random-Access memory or the like May. 27, 2003
6571325 Pipelined memory controller and method of controlling access to memory devices in a memory system May. 27, 2003
6571327 Non-aligned double word access in word addressable memory May. 27, 2003
6567335 Memory system having flexible bus structure and method May. 20, 2003
6567903 Data storage system having master/slave addressable memories May. 20, 2003
6567904 Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices May. 20, 2003
6564284 Apparatus for controlling a multibank memory device May. 13, 2003
6564306 Apparatus and method for performing speculative cache directory tag updates May. 13, 2003
6560686 Memory device with variable bank partition architecture May. 6, 2003
6557071 Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage Apr. 29, 2003
6553449 System and method for providing concurrent row and column commands Apr. 22, 2003
6553463 Method and system for high speed access to a banked cache memory Apr. 22, 2003
6549974 Semiconductor storage apparatus including a controller for sending first and second write commands to different nonvolatile memories in a parallel or time overlapped manner Apr. 15, 2003
6546453 Proprammable DRAM address mapping mechanism Apr. 8, 2003
6542957 Memory of controlling page mode access Apr. 1, 2003
6542959 Memory refreshing system Apr. 1, 2003
6539452 Semiconductor redundant memory provided in common Mar. 25, 2003
6539463 Disk-array apparatus capable of performing writing process in high transmission speed and surely avoiding data loss Mar. 25, 2003
6539474 System and method for selectively executing different boot routines depending on whether an error is detected Mar. 25, 2003
6535955 Redundant array of inexpensive disks controller Mar. 18, 2003
6535959 Circuit and method for reducing power consumption in an instruction cache Mar. 18, 2003
6535966 System and method for using a page tracking buffer to reduce main memory latency in a computer system Mar. 18, 2003
6532523 Apparatus for processing memory access requests Mar. 11, 2003

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