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Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory










Patents under this class:
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Patent Number Title Of Patent Date Issued
6745279 Memory controller Jun. 1, 2004
6742077 System for accessing a memory comprising interleaved memory modules having different capacities May. 25, 2004
6742098 Dual-port buffer-to-memory interface May. 25, 2004
6742105 Method and system for range matching May. 25, 2004
6738890 Data processor May. 18, 2004
6735664 Indirect addressing method and device incorporating the same May. 11, 2004
6732247 Multi-ported memory having pipelined data banks May. 4, 2004
6728851 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices Apr. 27, 2004
6728861 Queuing fibre channel receive frames Apr. 27, 2004
6725349 Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory Apr. 20, 2004
6725394 Media library with failover capability Apr. 20, 2004
6721843 Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible Apr. 13, 2004
6721860 Method for bus capacitance reduction Apr. 13, 2004
6717864 Latched sense amplifiers as high speed memory in a memory system Apr. 6, 2004
6718427 Method and system utilizing data fragments for efficiently importing/exporting removable storage volumes Apr. 6, 2004
6715014 Module array Mar. 30, 2004
6715024 Multi-bank memory device having a 1:1 state machine-to-memory bank ratio Mar. 30, 2004
6715025 Information processing apparatus using index and tag addresses for cache Mar. 30, 2004
6711654 Mechanism for bank conflict resolution for an out-of-order cache Mar. 23, 2004
6708263 Data transfer memory having the function of transferring data on a system bus Mar. 16, 2004
6704834 Memory with vectorial access Mar. 9, 2004
6701419 Interlaced memory device with random or sequential access Mar. 2, 2004
6697909 Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory Feb. 24, 2004
6694421 Cache memory bank access prediction Feb. 17, 2004
6690615 Semiconductor integrated circuit device Feb. 10, 2004
6691224 Computer system for accessing initialization data and method therefor Feb. 10, 2004
6687181 Semiconductor memory device with less data transfer delay time Feb. 3, 2004
6678204 Semiconductor memory device with high-speed operation and methods of using and designing thereof Jan. 13, 2004
6675255 Device initialize command for a synchronous memory Jan. 6, 2004
6675269 Semiconductor device with memory controller that controls page mode access Jan. 6, 2004
6675272 Method and apparatus for coordinating memory operations among diversely-located memory components Jan. 6, 2004
6671768 System and method for providing dynamic configuration ROM using double image buffers for use with serial bus devices Dec. 30, 2003
6668308 Scalable architecture based on single-chip multiprocessing Dec. 23, 2003
6668311 Method for memory allocation and management using push/pop apparatus Dec. 23, 2003
6665768 Table look-up operation for SIMD processors with interleaved memory systems Dec. 16, 2003
6662261 Data processing arrangement and method for connecting storage elements and groups selectively to processing circuits Dec. 9, 2003
6662264 File memory device and information processing apparatus using the same Dec. 9, 2003
6662266 Synchronous DRAM modules with multiple clock out signals Dec. 9, 2003
6658523 System latency levelization for read data Dec. 2, 2003
6654848 Simultaneous execution command modes in a flash memory device Nov. 25, 2003
6647455 On-die cache memory with repeaters Nov. 11, 2003
6647475 Processor capable of enabling/disabling memory access Nov. 11, 2003
6647477 Transporting data transmission units of different sizes using segments of fixed sizes Nov. 11, 2003
6643730 CPU controlled memory controlling device for accessing operational information Nov. 4, 2003
6640295 Semiconductor circuit with address translation circuit that enables quick serial access in row or column directions Oct. 28, 2003
6640296 Data processing method and device for parallel stride access Oct. 28, 2003
6636935 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules Oct. 21, 2003
6633576 Apparatus and method for interleaved packet storage Oct. 14, 2003
6633947 Memory expansion channel for propagation of control and request packets Oct. 14, 2003
6633948 Stackable dual mode (registered/unbuffered) memory interface cost reduction Oct. 14, 2003

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