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Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory










Patents under this class:
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Patent Number Title Of Patent Date Issued
6842837 Method and apparatus for a burst write in a shared bus architecture Jan. 11, 2005
6842843 Digital data storage subsystem including arrangement for increasing cache memory addressability Jan. 11, 2005
6839266 Memory module with offset data lines and bit line swizzle configuration Jan. 4, 2005
6839797 Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem Jan. 4, 2005
6836831 Independent sequencers in a DRAM control structure Dec. 28, 2004
6834322 Nonvolatile semiconductor memory device having plural memory circuits selectively controlled by a master chip enable terminal or an input command and outputting a pass/fail result Dec. 21, 2004
6832293 Audio playback apparatus and method for resuming interrupted playback recording Dec. 14, 2004
6832303 Method and system for managing an allocation of a portion of a memory Dec. 14, 2004
6826680 Microcontroller with memory content dependent conditional command decoder for accessing different memory types Nov. 30, 2004
6823432 Method and apparatus for load distribution across memory banks with constrained access Nov. 23, 2004
6823438 Method for memory allocation and management using push/pop apparatus Nov. 23, 2004
6820182 Support for exhaustion recovery in a data processing system with memory mirroring Nov. 16, 2004
6820255 Method for fast execution of translated binary code utilizing database cache for low-level code correspondence Nov. 16, 2004
6806883 System and method for handling display device requests for display data from a frame buffer Oct. 19, 2004
6807602 System and method for mapping bus addresses to memory locations utilizing access keys and checksums Oct. 19, 2004
6807603 System and method for input/output module virtualization and memory interleaving using cell map Oct. 19, 2004
6804756 Synchronization circuit for read paths of an electronic memory Oct. 12, 2004
6804760 Method for determining a type of memory present in a system Oct. 12, 2004
6801979 Method and apparatus for memory control circuit Oct. 5, 2004
6801980 Destructive-read random access memory system buffered with destructive-read memory cache Oct. 5, 2004
6799252 High-performance modular memory system with crossbar connections Sep. 28, 2004
6795889 Method and apparatus for multi-path data storage and retrieval Sep. 21, 2004
6795911 Computing device having instructions which access either a permanently fixed default memory bank or a memory bank specified by an immediately preceding bank selection instruction Sep. 21, 2004
6792499 Dynamic swapping of memory bank base addresses Sep. 14, 2004
6792511 Dual cache module support for array controller Sep. 14, 2004
6788731 Flexible correlation and queueing in CDMA communication systems Sep. 7, 2004
6789155 System and method for controlling multi-bank embedded DRAM Sep. 7, 2004
6785780 Distributed processor memory module and method Aug. 31, 2004
6782451 Control circuit to allow the use of an unbuffered DIMM in a system with a registered-DIMM-only chipset Aug. 24, 2004
6782460 Pipelined memory controller and method of controlling access to memory devices in a memory system Aug. 24, 2004
6782466 Arrangement and method for accessing data in a virtual memory arrangement Aug. 24, 2004
6775752 System and method for efficiently updating a fully associative array Aug. 10, 2004
6771556 Single port random access memory equipped with a relief module to operate as a dual port shared memory Aug. 3, 2004
6772271 Reduction of bank switching instructions in main memory of data processing apparatus having main memory and plural memory Aug. 3, 2004
6772300 Method and apparatus for managing out of order memory transactions Aug. 3, 2004
6769047 Method and system for maximizing DRAM memory bandwidth through storing memory bank indexes in associated buffers Jul. 27, 2004
6766385 Device and method for maximizing performance on a memory interface with a variable number of channels Jul. 20, 2004
6766397 Controlling access to a storage device Jul. 20, 2004
6766429 Low cost and high RAS mirrored memory Jul. 20, 2004
6763421 Instruction pair detection and pseudo ports for cache array Jul. 13, 2004
6763423 Storage area network methods and apparatus for logical-to-physical block address mapping Jul. 13, 2004
6760743 Instruction memory system for multi-processor environment and disjoint tasks Jul. 6, 2004
6760805 Flash management system for large page size Jul. 6, 2004
6756987 Method and apparatus for interleaving read and write accesses to a frame buffer Jun. 29, 2004
6757791 Method and apparatus for reordering packet data units in storage queues for reading and writing memory Jun. 29, 2004
6757800 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices Jun. 29, 2004
6754783 Memory controller with power management logic Jun. 22, 2004
6751113 Arrangement of integrated circuits in a memory module Jun. 15, 2004
6748480 Multi-bank, fault-tolerant, high-performance memory addressing system and method Jun. 8, 2004
6745277 Intelligent interleaving scheme for multibank memory Jun. 1, 2004

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