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Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory










Patents under this class:
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Patent Number Title Of Patent Date Issued
7003618 System featuring memory modules that include an integrated circuit buffer devices Feb. 21, 2006
7003622 Semiconductor memory Feb. 21, 2006
7003630 Mechanism for proxy management of multiprocessor storage hierarchies Feb. 21, 2006
7003639 Memory controller with power management logic Feb. 21, 2006
7003640 Power-aware adaptation in an information server Feb. 21, 2006
7000062 System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices Feb. 14, 2006
7000089 Address assignment to transaction for serialization Feb. 14, 2006
6996607 Storage subsystem and method employing load balancing Feb. 7, 2006
6993637 Unified memory system for multiple processors and method for controlling the same Jan. 31, 2006
6985992 Wear-leveling in non-volatile storage systems Jan. 10, 2006
6986081 Block interleaving apparatus, block deinterleaving apparatus, block interleaving method and block deinterleaving method Jan. 10, 2006
6983345 Associative memory Jan. 3, 2006
6981068 Removable mother/daughter peripheral card Dec. 27, 2005
6981122 Method and system for providing a contiguous memory address space Dec. 27, 2005
6976145 Method and apparatus for automatically configuring data storage subsystems Dec. 13, 2005
6970968 Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module Nov. 29, 2005
6968402 System and method for storing chunks of first cache line and second cache line in a buffer in a first and second chunk order Nov. 22, 2005
6968419 Memory module having a memory module controller controlling memory transactions for a plurality of memory devices Nov. 22, 2005
6968440 Systems and methods for processor memory allocation Nov. 22, 2005
6965969 Non-uniform cache apparatus, systems, and methods Nov. 15, 2005
6965980 Multi-sequence burst accessing for SDRAM Nov. 15, 2005
6961805 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure Nov. 1, 2005
6959256 Universally accessible fully programmable memory built-in self-test (MBIST) system and method Oct. 25, 2005
6957310 Interleave address generation device and interleave address generation method Oct. 18, 2005
6954822 Techniques to map cache data to memory arrays Oct. 11, 2005
6954832 Interleaver for iterative decoder Oct. 11, 2005
6954837 Consolidation of allocated memory to reduce power consumption Oct. 11, 2005
6952745 Device and method for maximizing performance on a memory interface with a variable number of channels Oct. 4, 2005
6952752 File memory device and information processing apparatus using the same Oct. 4, 2005
6950920 Dual controller system for dynamically allocating control of disk units Sep. 27, 2005
6948027 Method and system for using dynamic random access memory as cache memory Sep. 20, 2005
6948028 Destructive-read random access memory system buffered with destructive-read memory cache Sep. 20, 2005
6948030 FIFO memory system and method Sep. 20, 2005
6948044 Methods and apparatus for storage virtualization Sep. 20, 2005
6948046 Access controller that efficiently accesses synchronous semiconductor memory device Sep. 20, 2005
6944731 Dynamic random access memory system with bank conflict avoidance feature Sep. 13, 2005
6944739 Register bank Sep. 13, 2005
6941416 Apparatus and methods for dedicated command port in memory controllers Sep. 6, 2005
6937247 Memory control device and method Aug. 30, 2005
6938129 Distributed memory module cache Aug. 30, 2005
6930900 Arrangement of integrated circuits in a memory module Aug. 16, 2005
6930903 Arrangement of integrated circuits in a memory module Aug. 16, 2005
6931479 Method and apparatus for multi-functional inputs of a memory device Aug. 16, 2005
6931498 Status register architecture for flexible read-while-write device Aug. 16, 2005
6931505 Distributed memory module cache command formatting Aug. 16, 2005
6931507 Memory allocation method using multi-level partition Aug. 16, 2005
6928459 Plurality of file systems using weighted allocation to allocate space on one or more storage devices Aug. 9, 2005
6925543 Burst transfer memory Aug. 2, 2005
6922758 Synchronous flash memory with concurrent write and read operation Jul. 26, 2005
6922770 Memory controller providing dynamic arbitration of memory commands Jul. 26, 2005

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