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Class Information
Number: 711/5
Name: Electrical computers and digital processing systems: memory > Addressing combined with specific memory configuration or system > For multiple memory modules (e.g., banks, interleaved memory)
Description: Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory










Patents under this class:
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Patent Number Title Of Patent Date Issued
7203794 Destructive-read random access memory system buffered with destructive-read memory cache Apr. 10, 2007
7197607 Non-volatile memory with concurrent write and read operation to differing banks Mar. 27, 2007
7194572 Memory system and method to reduce reflection and signal degradation Mar. 20, 2007
7194568 System and method for dynamic mirror-bank addressing Mar. 20, 2007
7191295 Sensing word groups in a memory Mar. 13, 2007
7191292 Logging of level-two cache transactions into banks of the level-two cache for system rollback Mar. 13, 2007
7188228 Hybrid mapping implementation within a non-volatile memory system Mar. 6, 2007
7185159 Technique for accessing memory in a data processing apparatus Feb. 27, 2007
7185139 Easy access port structure and access method Feb. 27, 2007
7181563 FIFO memory with single port memory modules for allowing simultaneous read and write operations Feb. 20, 2007
7174415 Specialized memory device Feb. 6, 2007
7171529 Single-chip microcomputer with read clock generating circuits disposed in close proximity to memory macros Jan. 30, 2007
7167967 Memory module and memory-assist module Jan. 23, 2007
7167942 Dynamic random access memory controller Jan. 23, 2007
7162608 Translation lookaside buffer-based memory system and method for use in a computer having a plurality of processor element Jan. 9, 2007
7162591 Processor memory having a dedicated port Jan. 9, 2007
7162568 Apparatus and method for flash ROM management Jan. 9, 2007
7162567 Memory hub and method for memory sequencing Jan. 9, 2007
7159067 Information processing apparatus using index and TAG addresses for cache Jan. 2, 2007
7159066 Precharge suggestion Jan. 2, 2007
7151683 High speed memory modules utilizing on-trace capacitors Dec. 19, 2006
7149874 Memory hub bypass circuit and method Dec. 12, 2006
7149842 Efficient utilization of shared buffer memory and method for operating the same Dec. 12, 2006
7149841 Memory devices with buffered command address bus Dec. 12, 2006
7149827 Methods and apparatus for tristate line sharing Dec. 12, 2006
7143236 Persistent volatile memory fault tracking using entries in the non-volatile memory of a fault storage unit Nov. 28, 2006
7143207 Data accumulation between data path having redrive circuit and memory device Nov. 28, 2006
7143185 Method and apparatus for accessing external memories Nov. 28, 2006
7140023 Symbolic buffer allocation in local cache at a network processing element Nov. 21, 2006
7139862 Interleaving method and apparatus with parallel access in linear and interleaved order Nov. 21, 2006
7137023 Auxiliary alarm clock system for a personal computer Nov. 14, 2006
7136978 System and method for using dynamic random access memory and flash memory Nov. 14, 2006
7133962 Circulator chain memory command and address bus topology Nov. 7, 2006
7133960 Logical to physical address mapping of chip selects Nov. 7, 2006
7133959 Data-driven information processing device and method to access multiple bank memories according to multiple addresses Nov. 7, 2006
7130967 Method and system for supplier-based memory speculation in a memory subsystem of a data processing system Oct. 31, 2006
7130229 Interleaved mirrored memory systems Oct. 31, 2006
7127564 Double buffered flash programming Oct. 24, 2006
7127547 Processor with multiple linked list storage feature Oct. 24, 2006
7126873 Method and system for expanding flash storage device capacity Oct. 24, 2006
7124263 Memory controller, semiconductor integrated circuit, and method for controlling a memory Oct. 17, 2006
7120727 Reconfigurable memory module and method Oct. 10, 2006
7120077 Memory module having a plurality of integrated memory components Oct. 10, 2006
7117307 Memory controlling apparatus performing the writing of data using address line Oct. 3, 2006
7117292 Apparatus and method to switch a FIFO between strobe sources Oct. 3, 2006
7117291 Memory with synchronous bank architecture Oct. 3, 2006
7114012 Computer system and method for migrating from one storage system to another Sep. 26, 2006
7111140 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices Sep. 19, 2006
7111107 Microcontroller with dedicated memory bank for servicing interrupts Sep. 19, 2006
7110321 Multi-bank integrated circuit memory devices having high-speed memory access timing Sep. 19, 2006

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