| |
 |
|
Class Information
Number: 711/215
Name: Electrical computers and digital processing systems: memory > Address formation > In response to microinstruction
Description: Subject matter wherein microcode is stored in memory
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7617382 |
Method and apparatus for decompressing relative addresses |
Nov. 10, 2009 |
| 7617400 |
Storage partitioning |
Nov. 10, 2009 |
| 7506128 |
Smart card with volatile memory file subsystem |
Mar. 17, 2009 |
| 7461205 |
Performing useful computations while waiting for a line in a system with a software implemented cache |
Dec. 2, 2008 |
| 7406569 |
Instruction cache way prediction for jump targets |
Jul. 29, 2008 |
| 7343471 |
Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assi |
Mar. 11, 2008 |
| 7146457 |
Content addressable memory selectively addressable in a physical address mode and a virtual address mode |
Dec. 5, 2006 |
| 7143265 |
Computer program product memory access system |
Nov. 28, 2006 |
| 7103749 |
System and method for managing memory |
Sep. 5, 2006 |
| 7069415 |
System and method to automatically stack and unstack Java local variables |
Jun. 27, 2006 |
| 7051138 |
Interrupt-processing system for shortening interrupt latency in microprocessor |
May. 23, 2006 |
| 7039789 |
Circular addressing algorithms providing increased compatibility with one or more higher-level programming languages |
May. 2, 2006 |
| 7010665 |
Method and apparatus for decompressing relative addresses |
Mar. 7, 2006 |
| 6986014 |
System and method for using a vendor-long descriptor in ACPI for the chipset registers |
Jan. 10, 2006 |
| 6957322 |
Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion |
Oct. 18, 2005 |
| 6934828 |
Decoupling floating point linear address |
Aug. 23, 2005 |
| 6851037 |
Method of utilization of a data storage array, and array controller therefor |
Feb. 1, 2005 |
| 6816889 |
Assignment of dual port memory banks for a CPU and a host channel adapter in an InfiniBand computing node |
Nov. 9, 2004 |
| 6816959 |
Memory access system |
Nov. 9, 2004 |
| 6792520 |
System and method for using a using vendor-long descriptor in ACPI for the chipset registers |
Sep. 14, 2004 |
| 6775756 |
Method and apparatus for out of order memory processing within an in order processor |
Aug. 10, 2004 |
| 6732258 |
IP relative addressing |
May. 4, 2004 |
| 6662292 |
Memory access system |
Dec. 9, 2003 |
| 6658553 |
Universal pointer implementation scheme for uniformly addressing distinct memory spaces in a processor's address space |
Dec. 2, 2003 |
| 6654868 |
Information storage and retrieval system |
Nov. 25, 2003 |
| 6618803 |
System and method for finding and validating the most recent advance load for a given checkload |
Sep. 9, 2003 |
| 6584557 |
Processor and method for generating a pointer |
Jun. 24, 2003 |
| 6567908 |
Method of and apparatus for processing information, and providing medium |
May. 20, 2003 |
| 6519692 |
Method for updating a pointer to access a memory address in a DSP |
Feb. 11, 2003 |
| 6470439 |
FIFO memory control circuit |
Oct. 22, 2002 |
| 6438680 |
Microprocessor |
Aug. 20, 2002 |
| 6415375 |
Information storage and retrieval system |
Jul. 2, 2002 |
| 6345336 |
Instruction cache memory includes a clock gate circuit for selectively supplying a clock signal to tag RAM to reduce power consumption |
Feb. 5, 2002 |
| 6311258 |
Data buffer apparatus and method for storing graphical data using data encoders and decoders |
Oct. 30, 2001 |
| 6272615 |
Data processing device with an indexed immediate addressing mode |
Aug. 7, 2001 |
| 6189086 |
Data processing apparatus |
Feb. 13, 2001 |
| 6173385 |
Address generator for solid state disk drive |
Jan. 9, 2001 |
| 6141740 |
Apparatus and method for microcode patching for generating a next address |
Oct. 31, 2000 |
| 6128723 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
Oct. 3, 2000 |
| 6088781 |
Stride instruction for fetching data separated by a stride amount |
Jul. 11, 2000 |
| 6081869 |
Bit-field peripheral |
Jun. 27, 2000 |
| 6023750 |
Microcontroller having dedicated hardware for memory address space expansion via auxilliary address signal generation |
Feb. 8, 2000 |
| 5966722 |
Method and apparatus for controlling multiple dice with a single die |
Oct. 12, 1999 |
| 5960467 |
Apparatus for efficiently providing memory operands for instructions |
Sep. 28, 1999 |
| 5903908 |
Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories |
May. 11, 1999 |
| 5881260 |
Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction |
Mar. 9, 1999 |
| 5835968 |
Apparatus for providing memory and register operands concurrently to functional units |
Nov. 10, 1998 |
| 5835971 |
Method and apparatus for generating addresses in parallel processing systems |
Nov. 10, 1998 |
| 5832534 |
Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories |
Nov. 3, 1998 |
| 5813045 |
Conditional early data address generation mechanism for a microprocessor |
Sep. 22, 1998 |
|
|
|
